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Preliminary Technical Data
FEATURES
High Precision ADCs Dual Channel, Simultaneous Sampling, 16-Bit - ADCs Third Independent ADC for Temperature Sensing Programmable ADC throughput from 1Hz to 8KHz On-Chip 5ppm/C Voltage Reference Current Channel Fully differential, Buffered Input Programmable Gain 1 to 512 ADC Input Range -200mV to +300mV Digital Comparators, with Current Accumulator Feature Voltage Channel Buffered, On-Chip attenuator for 12V battery Inputs Temperature Channel External and On-Chip Temperature Sensor Options Microcontroller ARM7TDMI Core, 16/32-bit RISC architecture 20.48MHz PLL with Programmable Divider PLL Input Source: On-Chip Precision Oscillator On-Chip Low-Power Oscillator External (32.768KHz) Watch Crystal JTAG Port supports code download and debug
MicroConverter(R) Integrated, Precision Battery Sensor ADUC7032
Memory 96k Bytes Flash/EE Memory, 6k Bytes SRAM 10KCycles Flash Endurance, 20 Years Flash Retention In-Circuit Download via JTAG and LIN 64 x 16bit Result FIFO for Current and Voltage ADC On-Chip Peripherals LIN 1.2, 1.3 and 2.0 (Slave) Compatible Support via UART with Hardware Synchronization Flexible Wake-up I/O Pin, Master/Slave SPI Serial I/O 9-Pin GPIO Port, 2 X General Purpose Timers Wake-up and Watchdog Timers Power Supply Monitor, On-Chip Power-On-Reset Power Operates directly from 12V Battery Supply Current Consumption Normal Mode 10mA at 10MHz Low Power Monitor Mode Package and Temperature Range 48 Pin LQFP 7X7 mm body package Fully specified for -40C to 105C operation APPLICATIONS Battery Sensing/Management for Automotive Systems
FUNCTIONAL BLOCK DIAGRAM
NTRST TCK TDI TDO TMS
PRECISION ANALOG ACQUISITION
IIN+ IINVBAT
BUF
PGA
16-BIT - ADC
2.5V LDO PSM POR
MEMORY 96KB FLASH 6KB RAM 128B ADC FIFO
RESET
RESULT ACCUMULATOR
DIGITAL COMPARATOR 16-BIT - ADC
ARM7TDMI MCU 20MHz
BUF
PRECISION OSC LOW POWER OSC ON-CHIP PLL
XTAL1 XTAL2
VTEMP GND_SW
MUX
BUF
16-BIT - ADC 2xTIMERS WDT W/U TIMER
TEMP SENSOR VREF
PRECISION REFERENCE
GPIO PORT UART PORT SPI PORT LIN
WU LIN
DGND
REG_AVDD
AGND
VDD
VSS
REG_DVDD
IO_VSS
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
Figure 1: ADUC7032 Functional Block Diagram
Rev. PrD
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GPIO_8
Preliminary Technical Data
TABLE OF CONTENTS
TABLE OF CONTENTS................................................... 2 ADUC7032 DATASHEET TABLES................................. 5 ADUC7032 DATASHEET FIGURES .............................. 7 ADUC7032SPECIFICATIONS ........................................ 8 ELECTRICAL SPECIFICATIONS............................................ 8 TIMING SPECIFICATIONS ................................................. 15 SPI Timing Specifications........................................... 15 LIN Timing Specifications .......................................... 19 SPECIFICATION TERMINOLOGY............................. 21 ABSOLUTE MAXIMUM RATINGS ............................ 22 ORDERING GUIDE ........................................................... 22 ESD Caution............................................................... 22 PIN FUNCTION DESCRIPTIONS ............................... 23 ADUC7032 GENERAL DESCRIPTION....................... 26 OVERVIEW OF THE ARM7TDMI CORE ........................... 26 ARM7 Exceptions ....................................................... 27 ARM Registers............................................................ 27 Interrupt latency......................................................... 28 MEMORY ORGANISATION ................................................ 28 Memory Format.......................................................... 28 SRAM.......................................................................... 28 Remap......................................................................... 29 Remap operation ........................................................ 29 SYSMAP0 Register :................................................... 29 ADUC7032 RESET.......................................................... 30 RSTCLR Register : ..................................................... 30 RSTSTA Register : ...................................................... 30 FLASH/EE MEMORY AND THE ADUC7032...................... 31 FLASH/EE MEMORY CONTROL INTERFACE...................... 31 FEE0CON and FEE1CON Registers :....................... 32 FEE0STA and FEE1STA Registers :........................... 33 FEE0ADR and FEE1ADR Registers:......................... 33 FEE0DAT and FEE1DAT Registers:.......................... 33 FEE0MOD and FEE1MOD Registers : ..................... 34 FLASH/EE MEMORY SECURITY ........................................ 34 Block0, Flash/EE Memory Protection Registers :...... 35 Block1, Flash/EE Memory Protection Registers :...... 35 FLASH/EE MEMORY RELIABILITY .................................. 36 CODE EXECUTION TIME FROM SRAM AND FLASH/EE 37 Execution from SRAM ................................................ 37 Execution from Flash/EE ........................................... 37 ADUC7032 KERNEL ....................................................... 38 MEMORY MAPPED REGISTERS ........................................ 40 16-BIT - ANALOG TO DIGITAL CONVERTERS. 45 CURRENT CHANNEL ADC (I-ADC) ................................ 45
Rev. PrD | Page 2 of 128
ADUC7032
VOLTAGE CHANNEL ADC (V-ADC)................................46 TEMPERATURE CHANNEL ADC (T-ADC) ........................46 ADC GROUND SWITCH ...................................................47 ADC NOISE PERFORMANCE TABLES ...............................48 ADC MMR INTERFACE...................................................49 ADC Status Register : .................................................49 ADC Interrupt Mask Register :...................................50 ADC Mode Register : .................................................51 Current Channel ADC Control Register :...................52 Voltage Channel ADC Control Register : ...................53 Temperature Channel ADC Control Register : ...........54 ADC Filter Register : .................................................55 ADC Configuration Register : ....................................57 Current Channel ADC Data Register :.......................58 Voltage Channel Data Register: .................................58 Temperature Channel ADC Data Register : ...............58 ADC FIFO Register : .................................................58 Current Channel ADC Offset Calibration Register :..58 Voltage Channel Offset Calibration Register : ...........58 Temperature Channel Offset Calibration Register: ....58 Current Channel ADC Gain Calibration Register : ...59 Voltage Channel Gain Calibration Register :.............59 Temperature Channel Gain Calibration Register :.....59 Current Channel ADC Result Counter Limit Register: ....................................................................................59 Current Channel ADC Result Count Register: ...........59 Current Channel ADC Threshold Register:................59 Current Channel ADC Threshold Count Limit Register: ....................................................................................59 Current Channel ADC Threshold Count Register: .....60 Current Channel ADC Accumulator Register: ...........60 Current Channel ADC Accumulator Threshold Register: .....................................................................60 Low Power Voltage Reference Scaling Factor............60 ADC POWER MODES OF OPERATION...............................60 ADC Startup Procedure ..............................................60 ADC Normal Power Mode..........................................61 ADC Low Power Mode...............................................61 ADC Low Power-Plus Mode.......................................61 ADC Sinc3 Digital Filter Response ............................61 ADC Calibration.........................................................64 Using the Offset and Gain Calibration Registers .......64 Understanding the Offset and Gain Calibration Registers .....................................................................65 ADC DIAGNOSTICS.........................................................65 Current ADC Diagnostics...........................................65 Temperature ADC Diagnostics ...................................66 POWER SUPPLY SUPPORT CIRCUITS.....................67 ADUC7032 SYSTEM CLOCKS .....................................68 PLLSTA Register : ......................................................69 PLLCON Pre-write Key PLLKEY0: ...........................70
Preliminary Technical Data
PLLCON Pre-write Key PLLKEY1: ........................... 70 PLLCON Register : .................................................... 70 POWCON Pre-write Key POWKEY0: ....................... 70 POWCON Pre-write Key POWKEY1: ....................... 70 POWCON Register : .................................................. 71 ADUC7032 LOW POWER CLOCK CALIBRATION ............. 72 OSC0TRM Register :.................................................. 73 OSC0CON Register : ................................................. 73 OSC0STA Register : ................................................... 74 OSC0VAL0 Register :................................................. 74 OSC0VAL1 Register :................................................. 74 PROCESSOR REFERENCE PERIPHERALS ............ 75 INTERRUPT SYSTEM ........................................................ 75 TIMERS ........................................................................... 77 TIMER0 - LIFE-TIME TIMER ............................................ 78 Timer0 Value Register : .............................................. 78 Timer0 Capture Register :.......................................... 78 Timer0 Control Register :........................................... 79 Timer0 Load Registers: .............................................. 79 Timer0 Clear Register :.............................................. 79 TIMER1 ........................................................................... 80 Timer1 Load Registers: .............................................. 80 Timer1 Clear Register :.............................................. 80 Timer1 Value Register : .............................................. 80 Timer1 Capture Register :.......................................... 81 Timer1 Control Register :........................................... 81 TIMER2 - WAKE-UP TIMER ............................................. 82 Timer2 Load Registers: .............................................. 82 Timer2 Clear Register :.............................................. 82 Timer2 Value Register : .............................................. 82 Timer2 Control Register :........................................... 83 TIMER3 - WATCHDOG TIMER........................................... 84 Timer3 Load Register :............................................... 84 Timer3 Value Register : .............................................. 84 Timer3 Clear Register :.............................................. 85 Timer3 Control Register :........................................... 85 GENERAL PURPOSE I/O ............................................. 86 GPIO Port0 Control Register : .................................. 88 GPIO Port1 Control Register : .................................. 89 GPIO Port2 Control Register : .................................. 89 GPIO Port0 Data Register :....................................... 90 GPIO Port1 Data Register :....................................... 91 GPIO Port2 Data Register :....................................... 92 GPIO Port0 Set Register :.......................................... 93 GPIO Port1 Set Register :.......................................... 94 GPIO Port2 Set Register :.......................................... 94 GPIO Port0 Clear Register : ..................................... 95 GPIO Port1 Clear Register : ..................................... 95 GPIO Port2 Clear Register : ..................................... 96 HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE .................................................................... 97 High Voltage Interface Control Register :.................. 98 High Voltage Data Register: ...................................... 99
ADUC7032
High Voltage Configuration0 Register : ................... 100 High Voltage Configuration1 Register : ................... 101 High Voltage Interrupt Status Register :................... 102 High Voltage Monitor Register :............................... 103 WAKE-UP(WU)............................................................. 104 Wake-Up(WU) Pin Circuit Description .................... 104 HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE................................ 105 LOW VOLTAGE FLAG ( LVF )......................................... 105 HIGH VOLTAGE DIAGNOSTICS....................................... 105 UART SERIAL INTERFACE....................................... 106 BAUD RATE GENERATION .............................................. 106 Normal 450 UART baud rate generation. ................ 106 ADUC7032 Fractional divider: ................................ 106 UART REGISTER DEFINITION ........................................ 107 UART TX Register:.................................................. 107 UART RX Register:.................................................. 107 UART Divisor Latch Register 0:............................... 107 UART Divisor Latch Register 1:............................... 107 UART Control Register 0: ....................................... 108 UART Control Register 1: ....................................... 109 UART Status Register 0:.......................................... 109 UART Interrupt Enable Register 0:.......................... 110 UART Interrupt Identification Register 0:................ 110 UART Fractional Divider Register: ..........................111 SERIAL PERIPHERAL INTERFACE ........................ 112 SPI Control Register : .............................................. 113 SPI Status Register : ................................................. 114 SPI Receive Register : .............................................. 114 SPI Transmit Register :............................................. 114 SPI Divider Register : .............................................. 114 LIN (LOCAL INTERCONNECT NETWORK ) INTERFACE .................................................................. 115 LIN MMR DESCRIPTION .............................................. 115 LIN Hardware Synchronization Status Register :..... 116 LIN Hardware Synchronization Control Register 0: 117 LIN Hardware Synchronization Control Register 1: 118 LIN Hardware Synchronization Timer0 Register : ... 118 LIN Hardware Break Timer1 Register :.................... 119 LIN HARDWARE INTERFACE ......................................... 119 LIN Frame Protocol ................................................. 119 LIN Frame Break Symbol ......................................... 120 LIN Frame Synchronization Byte ............................. 120 LIN Frame Protected Identifier ................................ 120 LIN Frame Data Byte ............................................... 121 LIN Frame Data Transmission and Reception ......... 121 Example LIN Hardware Synchronization Routine.... 122 LIN Diagnostics........................................................ 123 ADUC7032 ON-CHIP DIAGNOSTICS ....................... 124 ADC Diagnostics ...................................................... 124 High Voltage I/O Diagnostics................................... 124 PART IDENTIFICATION ............................................ 125
Rev. PrD | Page 3 of 128
Preliminary Technical Data
System Serial ID Register 0: .................................... 125 System Serial ID Register 1: .................................... 126 System Kernel Checksum: ........................................ 126
ADUC7032
System Identification FEE0ADR: .............................127 OUTLINE DIMENSIONS.............................................128
Rev. PrD | Page 4 of 128
Preliminary Technical Data
ADUC7032 DATASHEET TABLES
Table 1 : ADUC7032--SPECIFICATIONS Table 2 : SPI Master Mode Timing (PHASE Mode = 1) Table 3 : SPI Master Mode Timing (PHASE Mode = 0) Table 4 : SPI Slave Mode Timing (PHASE Mode = 1) Table 5 : SPI Slave Mode Timing (PHASE Mode = 0) Table 6. Absolute Maximum Ratings (TA = -40C to 105C unless otherwise noted) Table 7: Pin Function Descriptions Table 8: SYSMAP0 MMR Bit Designations Table 9 : Device RESET Implications Table 10: RSTSTA/RSTCLR MMR Bit Designations Table 11: Command Codes in FEE0CON and FEE1CON Table 12: FEE0STA and FEE1STA MMR bit designations 8 15 16 17 18 22 23 29 30 30 32 33
ADUC7032
Table 29 : Allowable Combinations of SF and AF Table 30: ADCCFG MMR Bit Designations Table 31 : Allowable Combinations of SF and AF Table 32 : Common ADCFLT Configurations Table 33: Current ADC Diagnostics Table 34: Temperature ADC Diagnostics Table 35 : PLLSTA MMR Bit Description Table 36: PLLCON MMR Bit description Table 37 : POWCON MMR bit designations Table 38 : OSC0TRM MMR Bit Definition Table 39: OSC0CON MMR Bit Definition Table 40 : OSC0STA MMR Bit Definition Table 41 : IRQ/FIQ MMRs bit description Table 42 : SWICFG MMR Bit Descriptions Table 43 : Timer Event Capture Table 44 : T0CON MMR Bit Descriptions Table 45 : T1CON MMR Bit Descriptions Table 46 : T2CON MMR Bit Descriptions Table 47 : T3CON MMR Bit Definition Table 48 : External GPIO Pin to Internal Port Signal Assignments Table 49 : GP0CON MMR Bit Designations Table 50 : GP1CON MMR Bit Designations Table 51 : GP2CON MMR Bit Designations Table 52 : GP0DAT MMR Bit Descriptions Table 53 : GP1DAT MMR Bit Descriptions Table 54 :GP2DAT MMR Bit Descriptions Table 55 : GP0SET MMR Bit Descriptions Table 56 : GP1SET MMR Bit Descriptions Table 57 : GP2SET MMR Bit Descriptions Table 58 : GP0CLR MMR Bit Descriptions
56 57 61 63 66 66 69 70 71 73 73 74 75 76 77 79 81 83 85 87 88 89 89 90 91 92 93 94 94 95
Table 13: FEE0MOD and FEE1MOD MMR bit designations 34 Table 14: FEE0HID and FEE0PRO MMR bit designations Table 15: FEE1HID and FEE1PRO MMR bit designations Table 16: Typical execution cycles in ARM/Thumb mode Table 17 : Complete MMR List Table 18 : GND_SW Configuration 35 35 37 41 47
Table 19 : Current Channel ADC, Normal Power Mode, Typical Output RMS Noise (V) 48 Table 20 : Voltage Channel ADC, Typical Output RMS Noise (referred to ADC Voltage attenuator Input)(V) 48 Table 21 : Temperature Channel ADC, Typical Output RMS Noise (V) 48 Table 22 : ADCSTA MMR Bit Designations Table 23 : ADCMDE MMR Bit Designations Table 24 : ADC0CON MMR Bit Designations Table 25 : ADC1CON MMR Bit Designations Table 26 : ADC2CON MMR Bit Designations Table 27 : ADCFLT MMR Bit Designations Table 28 : ADC Conversion Rates and Settling Times 49 51 52 53 54 55 56
Rev. PrD | Page 5 of 128
Preliminary Technical Data
Table 59 : GP1CLR MMR Bit Descriptions Table 60 : GP2CLR MMR Bit Descriptions Table 61: HVCON MMR Write Bit Designations Table 62: HVCON MMR Read Bit Designations Table 63: HVDAT MMR Bit Designations Table 64: HVCFG0 Bit Designations Table 65: HVCFG1 Bit Designations Table 66: HVSTA Bit Designations Table 67: HVMON Bit Designations Table 68: High Voltage Diagnostics 95 96 98 98 99 100 101 102 103 105 Table 74 : COMIEN0 MMR Bit Descriptions Table 75 : COMIID0 MMR Bit Descriptions Table 76 : COMDIV2 MMR Bit Descriptions Table 77 : SPI Output Pins
ADUC7032
110 110 111 112 112 113 114 116 117 118 125 126 127
Table 78: SPI speed vs. clock divider bits in master mode Table 79 : SPICON MMR Bit Descriptions Table 80 : SPISTA MMR Bit Descriptions Table 81 : LHSSTA MMR Bit Descriptions Table 82 : LHSCON0 MMR Bit Descriptions Table 83 : LHSCON1 MMR Bit Descriptions Table 84 : SYSSER0 MMR Bit Descriptions Table 85: SYSSER1 MMR Bit Descriptions Table 86: FEE0ADR System Identification MMR Bit Descriptions
Table 69 : Baud rate using the standard Baud rate generator 106 Table 70: Baud rate using the Fractional Baud rate generator 106 Table 71 : COMCON0 MMR Bit Descriptions Table 72 : COMCON1 MMR Bit Descriptions Table 73: COMSTA0 MMR Bit Descriptions 108 109 109
Rev. PrD | Page 6 of 128
Preliminary Technical Data
ADUC7032 DATASHEET FIGURES
Figure 1: ADUC7032 Functional Block Diagram..........................1 Figure 2. SPI Master Mode Timing (PHASE Mode = 1)............15 Figure 3. SPI Master Mode Timing (PHASE Mode = 0)............16 Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)...............17 Figure 5 : SPI Slave Mode Timing (PHASE Mode = 0)..............18 Figure 6 : LIN V1.3 Timing Specification ....................................19 Figure 7 : LIN V2.0 Timing Specification ....................................20 Figure 8 : Package Pin Configuration...........................................22 Figure 9: ADUC7032 Register Organization................................27 Figure 10: Little Endian Format ....................................................28 Figure 11: ADUC7032 Memory Map...........................................28 Figure 12. Flash/EE Memory Data Retention .............................36 Figure 13: ADUC7032 Kernel Flowchart......................................39 Figure 14: Top Level MMR Map ...................................................40 Figure 15: Current ADC, Top Level Overview............................45 Figure 16 : Voltage/ Temperature ADC, Top Level Overview...46 Figure 17 : Example External Temperature Sensor Circuits......47 Figure 18: Internal Ground Switch Configuration .....................47 Figure 19 : Typical Digital Filter Response at FADC=1.0kHz (ADCFLT = 0x0007) ..............................................................62 Figure 20 : ModifiedSinc3 Digital Filter Response at FADC=1.0kHz (ADCFLT = 0x0087)...................................62 Figure 21 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x0000) ..............................................................62 Figure 22 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x4000) ..............................................................62 Figure 23 Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x961F)..............................................................63
ADUC7032
Figure 24 : Typical Digital Filter Response at FADC=4Hz, (ADCFLT = 0xBF1D) ............................................................63 Figure 25 : Typical Digital Filter Response at FADC=1Hz, (ADCFLT = 0xBD1F..............................................................63 Figure 26: Typical Power-On Cycle ..............................................67 Figure 27: ADUC7032 System Clock Generation .......................68 Figure 28 : Example OSC0TRM Calibration Routine................72 Figure 29: Interrupt Structure .......................................................76 Figure 30 : Timer 0 block diagram................................................78 Figure 31 : Timer 1 Block Diagram ..............................................80 Figure 32 : Timer 2 block diagram................................................82 Figure 33 : Timer3 Block Diagram ..............................................84 Figure 34 : ADUC7032 GPIO.........................................................86 Figure 35 : High Voltage Interface, Top Level Block Diagram..97 Figure 36 : WU Circuit, Block Diagram ....................................104 Figure 37 : Fractional Divider Baud Rate generation...............106 Figure 38 : LIN I/O, Block Diagram ...........................................115 Figure 39 : LIN Interface Timing ...............................................119 Figure 40 : LIN Break Field..........................................................120 Figure 41 : LIN Synch byte Field .................................................120 Figure 42 : LIN Identifier Byte Field...........................................120 Figure 43 : LIN Data Byte Field...................................................121 Figure 44 : Example LIN Configuration ....................................123 Figure 45 : 48-Lead, Plastic Quad Flat Pack, (LQFP-48), Dimensions shown in millimeters .....................................128
Rev. PrD | Page 7 of 128
Preliminary Technical Data
ADUC7032SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Table 1 : ADUC7032--SPECIFICATIONS
ADUC7032
(VDD =3.5V to18V, VREF = 1.2 V Internal Reference, fCORE = 10.24MHz driven from external 32.768kHz watch crystal or on-chip precision oscillator, All specifications TA = -40C to 105C, unless otherwise noted.) Parameter Test Conditions/Comments Min Typ Max Unit ADC SPECIFICATIONS Hz Chop Off, ADC Normal Operating Mode 4 8000 Conversion Rate 1 Hz 4 2600 Chop On, ADC Normal Operating Mode Hz 1 650 Chop On, ADC Low Power Mode Current Channel No Missing Codes 1 Integral Nonlinearity 1, 2 Offset Error 2, 3, 4, 5 Offset Error 1, 3, 6 Offset Error Drift6 Offset Error Drift6 Offset Error Drift6 Total Gain Error 1, 3, 7, 8, 9 Total Gain Error 1, 3, 7, 9, 10 Total Gain Error 1, 3, 7, 9, 11 Gain Drift PGA Gain Mismatch Error Output Noise 1, 12
Valid for all ADC Update Rates and ADC Modes Chop Off, 1LSB = (36.6/Gain)V Chop On Chop off, Valid for ADC Gains of 4 - 64, Normal Mode Chop off. Valid for ADC Gains of 128 - 512, Normal Mode Chop On Normal Mode Low Power Mode Low Power-Plus Mode, using Precision Vref
16 -10 -2 10 3 0.5 0.03 30 10 0.1 0.2 0.2 3 0.1 60 100 0.6 0.8 2.0 2.5 14 1.25 0.35 0.1 16 -10 10 1 0.3 0.03 0.06 0.03 3 60 60 180 1600 60 +10 1 +0.25 +0.15 60 +10 +2
Bits PPM of FSR LSB V LSB/C nV/C nV/C % % % ppm/C % nV rms nV rms V rms V rms V rms V rms V rms V rms V rms V rms Bits ppm of FSR LSB LSB LSB/C % % ppm/C V rms V rms V rms V rms
-0.5 -2 -1
+0.5 +2 +1
4Hz Update Rate, Gain = 512, Chop Enabled 10Hz Update Rate, Gain = 512, Chop Enabled 1KHz Update Rate, Gain = 512 1KHz Update Rate, Gain = 32 1KHz Update Rate, Gain = 4 8KHz Update Rate, Gain = 32 8KHz Update Rate, Gain = 4 ADC Low Power Mode, FADC = 10Hz, Gain=128 ADC Low Power Mode, FADC = 1Hz, Gain=128 ADC Low Power-Plus Mode,FADC=1Hz,Gain=512 Voltage Channel 13 No Missing Codes 1 Integral Nonlinearity 1 Offset Error3, 5 Offset Error 1, 3 Offset Error Drift Total Gain Error1,3, 7, 14 Total Gain Error1,3, 7, 14 Gain Drift Output Noise1, 15 Valid at all ADC Update Rates Chop Off , 1 LSB16=439.5uV Chop On Chop Off Includes Resistor Mismatch Temperature Range = -25C to 65C Includes Resistor Mismatch Drift 4Hz Update Rate 10Hz Update Rate 1KHz Update Rate 8KHz Update Rate
90 150 0.9 1.2 2.8 3.5 21 1.9 0.5 0.15
-0.25 -0.15
90 90 270 2400
Rev. PrD | Page 8 of 128
Preliminary Technical Data
Parameter Temperature Channel No Missing Codes 1 Integral Nonlinearity 1 Offset Error3, 5,16, 17 Offset Error 1, 3 Offset Error Drift Total Gain Error1,3, 18, 19, 17 Gain Drift Output Noise1 ADC SPECIFICATIONS ANALOG INPUT Current Channel Absolute Input Voltage Range Input Voltage Range 20,21 Test Conditions/Comments Valid at all ADC Update Rates Chop Off , 1 LSB16=19.84uV Chop On Min 16 -10 -5 -0.2 1KHz Update Rate 10 3 1 0.03 0.06 3 7.5 Typ
ADUC7032
Max Unit Bits ppm of FSR LSB LSB LSB/C % ppm/C V rms
60 +10 5 +0.2 11.25
Internal VREF=1.2V Applies to both IIN+ and IINGain =122 Gain =222 Gain =422 Gain =8 Gain = 16 Gain = 32 Gain = 64 Gain = 128 Gain = 256 Gain = 512 -200 1.2 600 300 150 75 37.5 18.75 9.375 4.68 2.3 -3 0.5 4 0 to 28.8 VBAT = 18V 4 100 0 to VREF 2.5 100 5.5 7 1300 3 1.5 18 +300 mV mV mV mV mV mV mV mV mV mV nA nA V V A mV V nA
Input Leakage Current 1 Input Offset Current 1, 23 Voltage Channel Absolute Input Voltage Range Input Voltage Range VBAT Input Current Temperature Channel Absolute Input Voltage Range Input Voltage Range VTEMP Input Current1 VOLTAGE REFERENCE ADC Precision Reference Internal VREF Power Up Time1 Initial Accuracy1 Internal VREF Temperature Coefficient 1, 24 Long term stability25 External Reference Input Range 26 VREF Divide by 2 Initial Error1 ADC Low Power Reference Internal VREF Initial Accuracy Initial Accuracy10 Temperature Coefficient 1, 24
1.2 0.5 Measured at TA = 35C -0.15 -20 5 100 0.15 +20
V Ms % ppm/C ppm/1000h V % V % % ppm/C
0.1 0.1 1.2 Measured at TA = 35C Using ADCREF, measured at TA = 35C -5 -300
Rev. PrD | Page 9 of 128
1.3 0.3
5 0.1 150 +300
Preliminary Technical Data
Parameter RESISTIVE ATTENUATOR Divider Ratio Resistor Mismatch Drift ADC Ground Switch Resistance Input Current TEMPERATURE SENSOR27 Accuracy MCU in power down or standby mode MCU in power down or standby mode Temperature Range = -25C to 65C 3 2 Direct path to ground 20k Resistor selected 10 10 20 Test Conditions/Comments Min Typ
ADUC7032
Max Unit
24 3
ppm/C
30 6
k mA
C C
POWER-ON RESET (POR) POR Trip Level POR Hysteresis RESET Time-Out from POR LOW VOLTAGE FLAG (LVF) LVF Level POWER SUPPLY MONITOR (PSM) PSM Trip Level WATCHDOG TIMER (WDT) Timeout Period 1 Timeout Step Size FLASH/EE MEMORY1 Endurance28 Data Retention29 DIGITAL INPUTS Input Leakage Current Input Pull-up Current Input Capacitance Input Leakage Current Input Pull-down Current All digital inputs except NTRST Input (High) = REG_DVDD Input (Low) = 0V 1 20 10 1 55 10 80 A A pF A A 32.768Khz Clock, 256 pre-scale TJ = 85C 10,000 20 Cycles Years 32.768Khz Clock, 256 pre-scale 0.008 7.8 512 sec msec Refers to Voltage at VDD pin 6.0 V Refers to Voltage at VDD pin 1.9 2.1 2.3 V Refers to Voltage at VDD pin 2.85 3.0 300 20 3.15 V mV msec
10
NTRST Only :Input (Low) = 0V NTRST Only : Input (High) = REG_DVDD
30
10 100
Rev. PrD | Page 10 of 128
Preliminary Technical Data
Parameter LOGIC INPUTS 1 VINL, Input Low Voltage VINH, Input High Voltage CRYSTAL OSCILLATOR1 Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Capacitance XTAL2 Capacitance ON-CHIP OSCILLATORS Low Power Oscillator Accuracy30 Precision Oscillator Accuracy MCU CLOCK RATE 8 programmable core clock selections within this range (binary divisions 1,2,4,8.....64, 128) MCU START-UP TIME at Power-On after Reset Event From MCU Power-Down Oscillator Running Wakeup from Interrupt Wakeup from LIN Crystal Powered Down Wakeup from Interrupt Internal PLL Lock Time LIN I/O General Baud Rate VDD Input capacitance LIN comparator response timeError! Bookmark not defined. ILIN DOM MAX ILIN_PAS_REC ILIN_PAS_DOM
1
ADUC7032
Min Typ Max Unit
Test Conditions/Comments All Logic inputs
0.4 2.0
V V
0.8 1.7 12 12
V V pF pF
131.072 Includes drift data from 1000hr life-test -6 131.072 Includes drift data from 1000hr life-test -1.2 1.2 3
kHz % kHz %
0.160
10.24
20.48
MHz
Includes kernel power-on execution time Includes kernel power-on execution time
25 5
msec msec
2 2 500 1
msec msec msec msec
1000 Supply Voltage Range for which the LIN interface is functional Using 22Ohm resistor Current Limit for driver when LIN Bus is in dominant state. VBAT = VBAT (MAX) Driver Off ; 7.0V < VBUS < 18V ; VDD = VLIN -0.7V Input Leakage VLIN = 0V -1 40 7 5.5 38
20000 18 90
Bits/sec V pF s
200 20
mA A mA
Rev. PrD | Page 11 of 128
Preliminary Technical Data
Parameter ILIN_NO_GND31 VLIN_DOM1 VLIN_REC VHYS
1 1 1 1
ADUC7032
Min -1 Typ Max 1 0.4VDD 0.6VDD 0.475VDD 0.5 VDD 0.525VDD 0.175VDD 1.2 2 0.6 0.8 0.8 VDD 0 0 0.1VDD 0.1VDD 30 0.7 47 1 Unit mA V V V V V V V V V V V
Test Conditions/Comments Control Unit disconnected from ground GND = VDD ; 0V VLIN <18V ; VBAT = 12V LIN Receiver Dominant State, VDD > 7.0V LIN Receiver Recessive State, VDD > 7.0V LIN Receiver Centre Voltage, VDD > 7.0V LIN Receiver Hysteresis Voltage LIN Dominant Output Voltage. VDD 7V, RL 500 LIN Dominant Output Voltage. VDD 18V,RL 500
1
VLIN_CNT
VLIN_DOM_DRV_LOSUP VLIN_DOM_DRV_HISUP VLIN_DOM_DRV_LOSUP VLIN_DOM_DRV_HISUP VLIN_RECESSIVE VBAT-Shift31 GND-Shift Rslave VSerial Diode
31 31
LIN Dominant Output Voltage. VDD 7V, RL 1000 LIN Dominant Output Voltage. VDD 18V,RL 1000 LIN Recessive Output Voltage
1
Slave Termination Resistance Voltage Drop at the serial diode DSer_Int
20 0.4
K V
LIN I/O General Contd. Transmit Propagation Delay 1 VDDMIN = 7V 4 s
Bus Load Conditions ( CBUS || RBUS ): 1nF||1k ; 6.8nF|| 660 ; 10nF || 500 Symmetry of Transmit Propagation Delay1 Receive Propagation Delay 1 Symmetry of Receive Propagation Delay1 VDDMIN = 7V -2 2 s VDDMIN = 7V VDDMIN = 7V -2 2 6 s s
LIN V1.3 Specification
Bus Load Conditions ( CBUS || RBUS ) : 1nF||1k ; 6.8nF|| 660 ; 10nF || 500
dV dt
1
Slew Rate Dominant and recessive Edges VBAT = 18V Slew Rate Dominant and recessive Edges VBAT = 7V Symmetry of rising and falling edge VBAT = 18V Symmetry of rising and falling edge VBAT = 7V
Rev. PrD | Page 12 of 128
1
2
3
V/s
dV dt
tSYM tSYM1
1
0.5 -5 -4
3 5 4
V/s s s
Preliminary Technical Data
Parameter Test Conditions/Comments Min Typ
ADUC7032
Max Unit
LIN V2.0 Specification Bus Load Conditions ( CBUS || RBUS ) : 1nF||1k ; 6.8nF|| 660 ; 10nF || 500 D1 Duty Cycle 1 THREC(MAX) = 0.744 * VBAT THDOM(MAX) = 0.581 * VBAT VSUP = 7.0V...18V; tBIT = 50s D1 = tBUS_REC(MIN) / (2 * tBIT ) Duty Cycle 2 THREC(MIN) = 0..284 * VBAT THDOM(MIN) = 0.422 * VBAT VSUP = 7.0V...18V; tBIT = 50s D2 = tBUS_REC(MAX) / (2 * tBIT )
0.396
D2
0.581
Wake RL = 1kOhm, CBUS = 91nF, RLIMIT = 39Ohms VDD1 VOH32 VOL32 VIH VIL Monoflop Timeout Package Thermal Specifications Thermal Shutdown 33 Thermal Impedance (ja)34 48 LQFP, Stacked Die Top Die Bottom Die 140 150 160 C Supply Voltage Range for which the Wake Pin is functional Output High Level Output Low Level Input High Level Input Low Level Timeout Period
7 5 4.6
18 2 1.2 1.3
V V V V V sec
50 25
C/W C/W
POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) REG_DVDD, REG_AVDD 35 Power Consumption IDD - MCU Normal Mode36 IDD - MCU Normal Mode36 IDD - MCU Powered Down1
3.5 2.5
2.6
18 2.7
V V
MCU Clock Rate = 10.24MHz, ADC Off MCU Clock Rate = 20.48MHz, ADC Off ADC Low Power Mode, measured over an ambient temperature range of -10C to +40C (Continuous ADC Conversion ) ADC Low Power Mode, measured over an ambient temperature range of -40C to +85C (Continuous ADC Conversion )
10 20
20
mA mA
300
400
A
IDD-MCU Powered Down1
300
500
A
Rev. PrD | Page 13 of 128
Preliminary Technical Data
Parameter IDD - MCU Powered Down1 Test Conditions/Comments ADC Low Power-Plus Mode, measured over an ambient temperature range of -10C to +40C (Continuous ADC Conversion ) Average Current, Measured with Wake and Watchdog Timer clocked from Low Power Oscillator Average Current, Measured with Wake and Watchdog Timer clocked from Low Power Oscillator over an ambient temperature range of -10C to +40C Per ADC Min Typ
ADUC7032
Max Unit
520 120
700 300
A A
IDD - MCU Powered Down
IDD - MCU Powered Down1
120 1.7 0.5 400
175
A mA mA A
IDD - Current ADC IDD - Voltage/Temperature ADC IDD - Precision Oscillator
1 2 3
These numbers are not production tested but are guaranteed by design and/or characterization data at production release Valid for Current ADC Gain setting of PGA=4 to 64 These numbers include temperature drift 4 Tested at Gain Range=4, Self-Offset Calibration will remove this error. 5 Measured with an internal short after an initial offset calibration. 6 Measured with an internal short 7 These numbers include internal reference temperature drift. 8 Factory Calibrated at Gain = 1. 9 System calibration at specific gain range will remove the error at this gain range 10 When used in conjunction with ADCREF, the Low Power Mode Reference error MMR. 11 Using ADC Normal Mode Voltage Reference 12 Typical Noise in Low Power modes is measured with Chop enabled. 13 Voltage Channel Specifications include resistive attenuator input stage 14 System Calibration will remove this error 15 rms noise is referred to Voltage attenuator input, for example at FADC=1KHz, typical rms noise at the ADC input is 7.5uV, scaled by the attenuator (24) yields these input referred noise figures 16 ADC Self Offset calibration will remove this error. 17 Valid after an initial Self Calibration 18 Factory calibrated for the internal temperature sensor during final production test. 19 System Calibration will remove this error 20 In ADC Low Power Mode the input range is fixed at 9.375mV. In ADC Low Power Plus Mode the input range is fixed at 2.34375mV. 21 It is possible to extend the ADC input range by up to 10% by modifying the factory set value of the Gain Calibration register or using system calibration. This approach can also be used to reduce the ADC Input Range (LSB Size). 22 Limited by minimum absolute input voltage range. 23 Valid for a differential input less than 10mV 24 Measured using Box Method 25 The long-term stability specification is non cumulative. The drift in subsequent 1,000 hour periods is significantly lower than in the first 1,000 hour period. 26 References of up to REG_AVDD can be accommodated by enabling an internal Divide-by-2 27 Die Temperature. 28 Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 method A117 and measured at -40C, +25C and +125C. Typical endurance at 25C is 170,000 cycles. 29 Retention lifetime equivalent at junction temperature (Tj) = 85C as per JEDEC Std. 22 method A117. Retention lifetime will de-rate with junction temperature. 30 Low Power oscillator can be calibrated against either the precision oscillator or the external 32.768kHz crystal in user code 31 These numbers are not production tested, but are supported by LIN Compliance testing. 32 Specified after Rlimit of 39Ohms 33 The MCU core is not shutdown but an interrupt is generated, if enabled. 34 Thermal Impedance can be used to calculate the thermal gradient from ambient to die temperature. 35 Internal Regulated Supply available at REG_DVDD (ISOURCE =5mA), and REG_AVDD (ISOURCE =1mA) 36 Typical, additional supply current consumed during Flash memory program and erase cycles is 7mA and 5mA respectively.
Rev. PrD | Page 14 of 128
Preliminary Technical Data
TIMING SPECIFICATIONS
ADUC7032
SPI Timing Specifications
Table 2 : SPI Master Mode Timing (PHASE Mode = 1)
Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF
Description SCLOCK low pulsewidth SCLOCK high pulsewidth Data output valid after SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
Min
Typ (SPIDIV + 1) x tHCLK (SPIDIV + 1) x tHCLK
Max
Unit ns ns ns ns ns ns ns ns ns
SCLOCK (POLARITY = 0)
tSH
tSL tSR tSF
SCLOCK (POLARITY = 1)
tDAV
MOSI MSB
tDF
tDR
BITS 6 - 1 LSB
MISO
MSB IN
BITS 6 - 1
LSB IN
05994-002
tDSU
tDHD
Figure 2. SPI Master Mode Timing (PHASE Mode = 1)
Rev. PrD | Page 15 of 128
Preliminary Technical Data
Table 3 : SPI Master Mode Timing (PHASE Mode = 0)
ADUC7032
Min Typ (SPIDIV + 1) x tHCLK (SPIDIV + 1) x tHCLK Max Unit ns ns ns ns ns ns ns ns ns ns
Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF
Description SCLOCK low pulsewidth SCLOCK high pulsewidth Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
SCLOCK (POLARITY = 0)
tSH
tSL tSR tSF
SCLOCK (POLARITY = 1)
tDAV tDOSU
MOSI MSB
tDF
tDR
BITS 6 - 1 LSB
MISO
MSB IN
BITS 6 - 1
LSB IN
05994-003
tDSU
tDHD
Figure 3. SPI Master Mode Timing (PHASE Mode = 0)
Rev. PrD | Page 16 of 128
Preliminary Technical Data
Table 4 : SPI Slave Mode Timing (PHASE Mode = 1)
ADUC7032
Min Typ (SPIDIV + 1) x tHCLK (SPIDIV + 1) x tHCLK Max Unit ns ns ns ns ns ns ns ns ns ns ns
Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS
Description CS to SCLOCK edge SCLOCK low pulsewidth SCLOCK high pulsewidth Data output valid after SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH
tSL tSR tSF
SCLOCK (POLARITY = 1)
tDAV
MISO MSB
tDF
tDR
BITS 6 - 1 LSB
MOSI
MSB IN
BITS 6 - 1
LSB IN
05994-004
tDSU
tDHD
Figure 4. SPI Slave Mode Timing (PHASE Mode = 1)
Rev. PrD | Page 17 of 128
Preliminary Technical Data
Table 5 : SPI Slave Mode Timing (PHASE Mode = 0)
ADUC7032
Min Typ (SPIDIV + 1) x tHCLK (SPIDIV + 1) x tHCLK Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS
Description CS to SCLOCK edge SCLOCK low pulsewidth SCLOCK high pulsewidth Data output valid after SCLOCK edge Data input setup time before SCLOCK edge Data input hold time after SCLOCK edge Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge
CS
tSFS
SCLOCK (POLARITY = 0)
tCS
tSH
SCLOCK (POLARITY = 1)
tSL tSR tSF
tDOCS tDF
MISO MSB
tDAV tDR
BITS 6 - 1 LSB
MOSI
MSB IN
BITS 6 - 1
LSB IN
05994-005
tDSU
tDHD
Figure 5 : SPI Slave Mode Timing (PHASE Mode = 0)
Rev. PrD | Page 18 of 128
Preliminary Technical Data
LIN Timing Specifications
ADUC7032
Figure 6 : LIN V1.3 Timing Specification
Rev. PrD | Page 19 of 128
Preliminary Technical Data
RECESSIVE INPUT TO TRANSMITTING NODE
ADUC7032
tBIT tBIT tBIT
TRANSMIT
DOMINANT
tLIN_DOM (MAX)
tLIN_REC (MIN)
THRESHOLDS OF RECEIVING NODE 1
THREC (MAX) THDOM (MAX)
VSUP
(TRANSCEIVER SUPPLY OF TRANSMITTING NODE) THREC (MIN) THDOM (MIN) THRESHOLDS OF RECEIVING NODE 2
LIN BUS
tLIN_DOM (MIN)
tLIN_REC (MAX)
RxD
(OUTPUT OF RECEIVING NODE 1)
tRX_PDF
tRX_PDR
RxD
tRX_PDR tRX_PDF
05994-005
(OUTPUT OF RECEIVING NODE 2)
Figure 7 : LIN V2.0 Timing Specification
Rev. PrD | Page 20 of 128
Preliminary Technical Data
SPECIFICATION TERMINOLOGY
CONVERSION RATE: The conversion rate specifies the rate at which an output result is available from the ADC, once the ADC has settled. The sigma-delta conversion techniques used on this part mean that while the ADC front-end signal is over-sampled at a relatively high sample rate, a subsequent digital filter is employed to decimate the output to give a valid 16-Bit data conversion result at output rates from 1Hz to 8 KHz. It should also be noted that when software switches from one input to another (on the same ADC), the digital filter must first be cleared and then allowed to average a new result. Depending on the configuration of the ADC and the type of filter this can take multiple conversion cycles.
ADUC7032
OFFSET ERROR: This is the deviation of the first code transition ADC input voltage from the ideal first code transition.
OFFSET ERROR DRIFT: Offset Error Drift is the variation in absolute offset error with respect to temperature. This error is expressed as LSBs per C.
GAIN ERROR
This is a measure of the span error of the ADC. It is a measure of the difference between the measured and the ideal span between any two points in the transfer function.
OUTPUT NOISE: The output noise is specified as the standard deviation (or 1 X Sigma) of ADC output codes distribution collected when the ADC input voltage is at a dc voltage. It is expressed as rms. The output or RMS noise can be used to calculate the Effective Resolution of the ADC as defined by the following equation
INTEGRAL NON_LINEARITY (INL): This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition and full scale, a point 0.5 LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale.
Effective Resolution= Log 2 (Full-Scale Range / RMS Noise) Bits The peak-to-peak noise is defined as the deviation of codes that fall within 6.6 X Sigma of the distribution of ADC output codes collected when the ADC input voltage is at dc. The peak-topeak noise is therefore calculated as 6.6 times the RMS noise. The peak-to-peak noise can be used to calculate the ADC (Noise Free, Code) Resolution for which there will be no code flicker within a 6.6-Sigma limit as defined by the following equation Noise Free Code Resolution = Log 2 (Full-Scale Range / Peak to Peak Noise) Bits
NO MISSING CODES: This is a measure of the Differential Non-Linearity of the ADC. The error is expressed in bits and specifies the number of codes (ADC results) as 2^N Bits, where is N = No Missing Codes, guaranteed to occur through the full ADC input range.
Acronyms used in this Datasheet: ADC ARM JTAG LIN LSB LVF MCU MMR MSB PID POR PSM RMS Analog to Digital Converter Advanced RISC Machine Joint Test Action Group Local Interconnect Network Least Significant Byte/Bit Low Voltage Flag MicroController Memory Mapped Register Most Significant Byte/Bit Protected Identifier Power On Reset Power Supply Monitor Root Mean Square
Rev. PrD | Page 21 of 128
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 6. Absolute Maximum Ratings (TA = -40C to 105C unless otherwise noted)
Parameter AGND to DGND to VSS to IO_VSS VBAT to AGND VDD to VSS VDD to VSS for 1 second LIN to IO_VSS WU to IO_VSS Wake Continuous Current HV IO Pins Short Circuit Current Digital I/O Voltage to DGND VREF to AGND ADC Inputs to AGND ESD (HBM) Rating LIN, WU and VBAT All other pins Storage Temperature Range Junction Temperature (transient) Junction Temperature (continuous) Lead Temperature, Soldering Reflow (15 sec) Rating -0.3V to +0.3V -22V to 40V -0.3V to 33V -0.3V to 40V -16V to 40V -3V to 33V 50mA 100mA -0.3V to REG_DVDD +0.3 -0.3V to REG_AVDD + 0.3 -0.3V to REG_AVDD +0.3 4KV 2KV 125C 150C 130C 260C
ADUC7032
48
47 46
45
44
43 42 41 40
39
38 37
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
13 14
15 16 17
18 19
20
21 22
23
24
Figure 8 : Package Pin Configuration
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ESD Caution
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD | Page 22 of 128
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
Table 7: Pin Function Descriptions
ADUC7032
Pin#
Mnemonic
Type*
Function Reset Input Pin, Active Low. This pin has an internal, weak pull-up resistor to REG_DVDD. If this pin is not being used it can be left not connected. For added security and robustness, it is recommended that this pin be strapped via a resistor to REG_DVDD. General Purpose Digital I/O 5 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 3 states, namely: General Purpose Digital I/O 5 External Interrupt Request 1, Active High Receive Data for UART Serial Port This Pin may also be used as a clock input to Timer1. General Purpose Digital I/O 6 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 2 states, namely: General Purpose Digital I/O 6 Transmit Data for UART Serial Port General Purpose Digital I/O 7 is a multi-function pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 2 states, namely: General Purpose Digital I/O 7 External Interrupt Request 4, Active High General Purpose Digital I/O 8 is a multi-function pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 2 states, namely: General Purpose Digital I/O 8 External Interrupt Request 5, Active High This Pin may also be used as a clock input to Timer1. JTAG Test Clock. This clock input pin is one of the standard 5 pin JTAG debug port on the part. TCK is an input pin only and has an internal weak pull-up resistor. If not being used this pin can be left unconnected JTAG Test Data Input. This data input pin is one of the standard 5 pin JTAG debug port on the part. TDI is an input pin only and has an internal weak pullup resistor. If not being used this pin can be left unconnected Ground Reference for On-Chip Digital Circuits No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally JTAG Test Data Output. This data output pin is one of the standard 5 pin JTAG debug port on the part. TDO is an output pin only. On power-on this output is disabled and pulled high via an internal weak pull-up resistor. If not being used this pin can be left unconnected JTAG Test Reset. This Reset input pin is one of the standard 5 pin JTAG debug port on the part. NTRST is an input pin only and has an internal weak pulldown resistor. If not being used this pin can be left unconnected. NTRST is also monitored by the on-chip kernel to enable LIN boot-load mode. JTAG Test Mode Select. This Mode Select input pin is one of the standard 5 pin JTAG debug port on the part. TMS is an input pin only and has an internal weak pull-up resistor. If not being used this pin can be left unconnected
1
RESET
I
2
GPIO_5/IRQ1/RxD
I/O
3
GPIO_6/TxD
I/O
4
GPIO_7/IRQ4
I/O
5
GPIO_8/ IRQ5
I/O
6
TCK
I
7 8 9
TDI DGND NC
I S
10
TDO
O
11
NTRST
I
12
TMS
I
Rev. PrD | Page 23 of 128
Preliminary Technical Data
Pin# 13 14 Mnemonic VBAT VREF Type* I I Function
ADUC7032
Battery Voltage Input to resistor divider External Reference Input Terminal. If this input is not being used it should be connected directly to the AGND system ground Switch to internal analog ground reference. Negative input for external temperature channel and external reference If this input is not being used it should be connected directly to the AGND system ground. No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally External Pin for NTC/PTC temperature measurement Positive Differential Input for Current Channel Negative Differential Input for Current Channel Ground Reference for On-Chip Precision Analog Circuits Ground Reference for On-Chip Precision Analog Circuits No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally Nominal 2.6V output from on chip regulator No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally General Purpose Digital I/O 0 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 3 states, namely: General Purpose Digital I/O 0 External Interrupt Request 0, Active High SPI Interface, Slave Select Input General Purpose Digital I/O 1 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 2 states, namely: General Purpose Digital I/O 1 SPI Interface, Serial Clock Input General Purpose Digital I/O 2 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 2 states, namely: General Purpose Digital I/O 2 SPI Interface, Master Input/Slave Output Pin General Purpose Digital I/O 3 is a Multi-Function Pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used it can be left unconnected. This multi-function pin can be configured in one of 2 states, namely: General Purpose Digital I/O 3 SPI Interface, Master Output/Slave Input Pin General Purpose Digital I/O 4 is a programmable digital I/O pin. By default and after Power-On-Reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and if not being used this pin can be left unconnected. GPIO4 is can also be configured to output a 2.56MHz clock No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally
Rev. PrD | Page 24 of 128
15
GND_SW
S
16 17 18 19 20 21 22 23 24 25 26
NC NC VTEMP IIN+ IINAGND AGND NC REG_AVDD NC NC S I I I S S
27
GPIO_0/IRQ0/SS
I/O
28
GPIO_1/SCLK
I/O
29
GPIO_2/MIS0
I/O
30
GPIO_3/MOSI
I/O
31
GPIO_4/ECLK
I/O
32
NC
Preliminary Technical Data
Pin# 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
*
ADUC7032
Type* S S S O I Function Nominal 2.6V output from the on-chip regulator Ground Reference for On-Chip Digital Circuits Ground Reference for On-Chip Digital Circuits Crystal Oscillator Output. If an external Crystal is not being used, this pin can be left unconnected. Crystal Oscillator Input. If an external Crystal is not being used, this pin should be connected to the DGND system ground. No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally High Voltage Wake-Up Transmit pin. If this pin is not being used, it should not be connected externally. Battery Power Supply to on-chip regulator No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally Ground Reference for the internal Voltage Regulators No Connect, this pin is not connected internally but is reserved for possible future use, this pin should therefore not be connected externally This pin is reserved for HV-IO Output only functionality. This pin should connected externally to the IO_VSS ground reference Ground Reference for High Voltage I/O Pins LIN Serial Interface Input/Output Pin
Mnemonic REG_DVDD DGND DGND XTAL1 XTAL2 NC NC NC WU VDD NC VSS NC Reserved IO_VSS LIN
O S
S
S I/O
I = Input, O = Output, S = Supply No Connect ( NC ) pins may be grounded if required.
Rev. PrD | Page 25 of 128
Preliminary Technical Data
ADUC7032 GENERAL DESCRIPTION
ADUC7032
The ADUC7032 is a complete, system solution for battery monitoring in 12V automotive applications. The device integrates all of the required features to precisely and intelligently monitor, process and diagnose 12V battery parameters including battery current, voltage and temperature over a wide range of operating conditions. Minimizing external system components, the device is powered directly from the 12V battery. An on-chip LDO, Low DropOut, regulator generates the supply voltage for the three integrated 16-Bit - ADCs. The ADCs precisely measure battery current, voltage and temperature, which may be used to characterize the car battery's state of health and charge. A Flash/EE memory based ARM7 microcontroller (MCU) is also integrated on-chip and is used both to pre-process the acquired battery variables, and to manage communications from the ADUC7032 to the main Electronic Control Unit (ECU) via a Local Interconnect Network (LIN) interface, which is integrated on-chip. Both the MCU and the ADC sub-system can be individually configured to operate in normal or flexible power-saving modes of operation. In its normal operating mode the MCU is clocked indirectly from an on-chip oscillator via the Phase Locked Loop (PLL) at a maximum clock rate of 20.48MHz. In its power-saving operating modes, the MCU can be totally powered down, waking up only in response to an ADC conversion result ready, digital comparators, the wake-up timer, a POR or an external serial communication event. The ADC can be configured to operate in a normal (full power) mode of operation, interrupting the MCU after various sample conversion events. The Current Channel features two low power modes, Low Power and Low Power-Plus, generating conversion results to a lower performance specification. On-chip factory firmware supports in-circuit Flash/EE reprogramming via the LIN or JTAG serial interface ports while non-intrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart Development System supporting the ADUC7032. The ADUC7032 operates directly from the 12V battery supply and is fully specified over a temperature range of -40C to 105C. The ADUC7032 is functional, with degraded performance, at temperatures from 105C to 125C.
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit Reduced Instruction Set Computer (RISC), developed by ARM Ltd. The ARM7TDMI is a Von Neumann based architecture, which means that it uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16 or 32 bits and the length of the instruction word is either 16 bits or 32 bits, depending on which mode the core is operating in. The ARM7TDMI is an ARM7 core with 4 additional features: T D M I support for the Thumb (16 bit) instruction set. support for debug enhanced multiplier includes the EmbeddedICE module to support embedded system debugging.
Thumb mode (T)
An ARM instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, the Thumb instruction set. Faster code execution from 16-bit memory and greater code density can be achieved by using the Thumb instruction set, which makes the ARM7TDMI core particularly suited for embedded applications. However the Thumb mode has three limitations: - Relative to ARM, Thumb code usually requires more instructions to perform that same task. Therefore, ARM code is best for maximizing the performance of time-critical code. In most applications. - The Thumb instruction set does not include some instructions which are needed for exception handling, so ARM code may be required for exception handling. - When an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at this address. The first command is required to be in ARM code.
Multiplier (M)
The ARM7TDMI instruction set includes an enhanced multiplier, with four extra instructions which perform 32-bit by 32-bit multiplication with 64-bit result and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result.
Rev. PrD | Page 26 of 128
Preliminary Technical Data
EmbeddedICE (I)
The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers which allow non intrusive user code debugging. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers may be interrogated, as well as the Flash/EE, the SRAM and the Memory Mapped Registers.
ADUC7032
ARM Registers
The ARM7TDMI has 16 standard registers. R0-R12 are used for data manipulation, R13 is the stack pointer, R14 is the link register and R15 is the program counter which indicates the instruction currently being executed. The link register contains the address from which the user has branched, if the branch and link command was used, or the command during which an exception occurred. The stack pointer contains the current location of the stack. As a general rule of thumb on an ARM7TDMI, the stack starts at the top of the available RAM area, and descends, using the area as required. A separate stack is defined for each of the exceptions. The size of each stack is user configurable and is dependent on the target application. On the ADUC7032 the stack begins at 0x000417FC and descends. Whilst programming using high level languages, such as C, it may be possible to ensure that the stack does not overflow. This is dependent on the compiler used. When an exception occurs, some of the standard register are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 9. The FIQ mode has more registers (R8 to R12) supporting faster interrupt processing. With the increased number of non-critical registers, the interrupt may be processed without the need to save or restore these registers, which reduces the response time of the interrupt handling process. More information relative to the programmer's model and the ARM7TDMI core architecture can be found in the following documents available from ARM Ltd.: - DDI0029G, ARM7TDMI Technical Reference Manual. - DDI0100E, ARM Architecture Reference Manual..
R0 USABLE IN USER MODE SYSTEM MODES ONLY R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are: - Normal interrupt or IRQ. It is provided to service generalpurpose interrupt handling of internal and external events - Fast interrupt or FIQ. It is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ - Memory abort (Prefetch and Data) - Attempted execution of an undefined instruction - Software interrupt (SWI) instruction which can be used to make a call to an operating system. Typically the programmer will define interrupts as IRQ but for higher priority interrupts, the programmer can define interrupts as of type FIQ. The priority of the above exceptions and vector address are as follows: 1. 2. 3. 4. 5. 6. Hardware Reset Memory Abort ( Data ) FIQ IRQ Memory Abort ( Prefetch ) Software Interrupt and Undefined Instruction 0x00 0x10 0x1C 0x18 0x0C 0x08 0x04
A Software interrupt and an Undefined Instruction Note: exception have the same priority and are mutually exclusive. NOTE: The above list are located from 0x00 -0x1C, with a reserved location at 0x14. This location is required to be written with either 0x27011970 or the checksum of Page Zero, excluding location 0x14. If this is not done, user code will not be executed and LIN download mode will be entered. For more information please refer to the ADUC7032 LIN download Technote.
CPSR
SPSR_FIQ FIQ MODE
SPSR_SVC SVC MODE
SPSR_ABT
USER MODE
ABORT MODE
IRQ MODE
UNDEFINED MODE
Figure 9: ADUC7032 Register Organization
Rev. PrD | Page 27 of 128
05994-008
Preliminary Technical Data
Interrupt latency
The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an LDM) which loads all the registers including the PC, plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI will be executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just over 2.44S in a system using a continuous 20.48MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time may be reduced to 42 cycles if the LDM command is not used, some compilers have an option to compile without using this command. Another option is to run the part in THUMB mode where this is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is five cycles. This consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI will initially (1st instruction) run in ARM (32-bit) mode when an exception occurs. The user may immediately switch from ARM mode to Thumb mode if required, e.g. when executing interrupt service routines.
ADUC7032
Memory Format
The ADUC7032 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.
BIT 31 BYTE 3 . . . B 7 3 BYTE 2 . . . A 6 2 32 BITS BYTE 1 . . . 9 5 1 BIT 0 BYTE 0 . . . 8 4 0 0x00000004h 0x00000000h
05994-009
05994-011
0xFFFFFFFFh
Figure 10: Little Endian Format
RESERVED FFFF0FFFh FFFF0000h MMRs RESERVED 00097FFFh FLASH/EE 00080000h RESERVED 00417FFh 00040000h SRAM RESERVED 0017FFFh
MEMORY ORGANISATION
The ARM7, a Von Neumann architecture, MCU core sees memory as a linear array of 232 byte locations. As shown in Figure 11, the ADUC7032 maps this into 4 distinct user areas namely, a re-mappable memory area, an SRAM area, a Flash/EE area and a Memory Mapped Register (MMR) area. The first 96kBytes of this memory space is used as an area into which the on-chip Flash/EE or SRAM can be remapped. A second 4kByte area at the top of the memory map is used to locate the Memory Mapped Registers (MMR), through which all on-chip peripherals are configured and monitored. The remaining 2 areas of memory are constituted as 6kByte of SRAM and 96kByte of On-Chip Flash/EE memory. 94kByte of On-Chip Flash/EE memory are available to the user, and the remaining 2kBytes are reserved for the on-chip Kernel. These areas are described in more detail below. Any access, either reading or writing, to an area not defined in the memory map will result in a Data Abort exception.
00000000h
RE-MAPPABLE MEMORY SPACE (FLASH/EE OR SRAM)
Figure 11: ADUC7032 Memory Map
SRAM
6kBytes of SRAM are available to the user, organized as 1536 X 32 bits, i.e. 1536Words, which is located at 0x40000. The RAM space can be used as data memory and also as a volatile program space. ARM code can run directly from SRAM at full clock speed given that the SRAM array is configured as a 32-bit wide memory array. SRAM is read/writeable in 8/16/32 bit segments.
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Preliminary Technical Data
Remap
The ARM exception vectors are all situated at the bottom of the memory array, from address 0x00000000 to address 0x00000020. By default, after a reset, the Flash/EE memory is logically mapped to address 0x00000000. It is possible to logically REMAP the SRAM to address 0x00000000. This is done by a setting bit zero of the SYSMAP0 MMR, which is located at 0xFFFF0220. To revert Flash/EE to 0x00000000, bit zero of SYSMAP0 is cleared. It may be desirable to remap RAM to 0x00000000 to optimize the interrupt latency of the ADUC7032, as code may be run in full 32bit ARM mode and at the maximum core speed. It should be noted that when an exception occurs, the core will default to ARM mode.
ADUC7032
code. This so called kernel is hidden and cannot be accessed by user code. If the ADUC7032 is in normal mode, it will execute the power-on configuration routine of the kernel and then jump to the reset vector address, 0x00000000, to execute the users reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset routine must always be written in Flash/EE. Precaution must be taken to execute the REMAP command from the absolute Flash/EE address, and not from the mirrored, remapped segment of memory, as this will be replaced by the SRAM. If a remap operation is executed whilst operating code from the mirrored location, Prefetch/Data aborts may occur or the user may observe abnormal program operation. This operation is reversible: the Flash/EE memory may be remapped at address 0x00000000 by clearing bit zero of the SYSMAP0 MMR. Precaution must again be taken to execute the remap function from outside the mirrored area. Any kind of reset will logically remap the Flash/EE memory to the bottom of the memory array.
Remap operation
When a reset occurs on the ADUC7032, execution starts automatically in the factory programmed internal configuration
SYSMAP0 Register :
Name : Address : Default Value : Access : Function : memory Bit 7-1 0 SYSMAP0 0xFFFF0220 0x00 Read/Write Access This 8-bit register allows user code to remap either RAM or Flash/EE memory space into the bottom of the ARM space starting at location 0x00000000.
Table 8: SYSMAP0 MMR Bit Designations
Description Reserved These bits are reserved and should be written as 0 by user code Remap Bit. Set by the user to remap the SRAM to 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to 0x00000000.
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Preliminary Technical Data
ADUC7032 RESET
There are four kinds of reset: external reset, Power-on-reset, watchdog reset and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. The bits in this register can be cleared to `0' by writing to the RSTCLR MMR at
ADUC7032
0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA. These registers can be used during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset event are tabulated in Table 9 below.
Table 9 : Device RESET Implications
IMPACT RESET POR Watchdog Reset Software Reset External Reset Pin
Reset External Pins to Default State
Kernel Executed
Reset All External MMRs (excluding RSTSTA)
Reset All HV Indirect Registers
Peripherals Reset
RAM Valid
RSTSTA (Status after Reset Event)
Note 1
RSTSTA[0] =1 RSTSTA[1] =1 RSTSTA[2] =1 RSTSTA[3] =1
Note1: If LVF is enabled(HVCFG0[2]), RAM has not been corrupt by the POR reset mechanism if LVF Status bit HVSTA[6] is `1'.
RSTCLR Register :
Name : Address : Default Value : Access : Function : RSTCLR 0xFFFF0234 0x00 Write Only This 8-bit write only register clears the corresponding bit in RSTSTA.
RSTSTA Register :
Name : Address : Default Value : Access : Function : RSTSTA 0xFFFF0230 0x01 Read/Write Access This 8-bit register indicates the source of the last reset event and can also be written by user code to initiate a software reset.
Table 10: RSTSTA/RSTCLR MMR Bit Designations
Bit 7-4 3
Description Not Used These bits are not used and will always read as `0' External Reset Set to 1 automatically when an external reset occurs Cleared by setting the corresponding bit in RSTCLR Software Reset Set to `1' by user code to generate a software reset. Cleared by setting the corresponding bit in RSTCLR Watchdog timeout Set to 1 automatically when a watchdog timeout occurs Cleared by setting the corresponding bit in RSTCLR Power-on-reset Set automatically when a power-on-reset occurs Cleared by setting the corresponding bit in RSTCLR
2
1
0
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Preliminary Technical Data
FLASH/EE MEMORY AND THE ADUC7032
The ADUC7032 incorporates Flash/EE memory technology onchip to provide the user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased, the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes non-volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADUC7032 Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes. battery parameter data.
ADUC7032
It is possible to write to a single 16 bit location only twice between erases, i.e. It is possible to walk bytes, not bits. If a location is written to more than twice, then it is possible that the contents of the Flash/EE page may be corrupted. The 94kBytes of Flash/EE memory can be programmed incircuit, using a serial download mode via the LIN interface or the integrated JTAG port.
(1) Serial Downloading (In-Circuit Programming)
The ADUC7032 facilitates code download via the LIN pin.
(2) JTAG access
The ADUC7032 features an on-chip JTAG Debug Port to facilitate code download and debug.
FLASH/EE MEMORY CONTROL INTERFACE
The access to and control of the Flash/EE memory on the ADUC7032 is managed by an on-chip memory controller. The controller manages the Flash/EE memory as two separate blocks (0 and 1). Block 0 consists of the 32KB Flash/EE memory mapped from 0x0009 0000 to 0x0009 7FFF (including the 2KB kernel space which is reserved at the top of this block). Block 1 consists of the 64KB Flash/EE memory mapped from from 0x0008 0000 to 0x0008 FFFF. It should be noted that MCU core can continue to execute code from one memory block while an active erase or program cycle is being carried out on the other block. If a command operates on the same block as the code currently executing, the core is halted until the command is completed, this also applies to code execution. User Code, LIN and JTAG programming use the Flash/EE memory Control Interface, which consists of the following MMRs : - FEExSTA (x= 0 or 1): read only register, reflects the status of the Flash Control Interface - FEExMOD (x= 0 or 1): sets the operating mode of the Flash Control Interface - FEExCON (x= 0 or 1): 8-bit command register. The commands are interpreted as described in Table 11. - FEExDAT (x= 0 or 1): 16-bit data register. - FEExADR (x= 0 or 1): 16-bit address register. - FEExSIGN (x= 0 or 1): Holds the 24-bit code signature as a result of the signature command being initiated. - FEExHIDE (x= 0 or 1): Protection MMR. Controls read and write protection of the Flash memory code space. If previously configured via the FEEPRO register, FEEHIDE may require a software key to enable access.
Flash/EE Memory
The total 96kBytes of Flash/EE memory are organized as 48k X 16 bits. 94kBytes are user space and 2kBytes are reserved for boot loader/kernel space. The page size of this Flash/EE memory is 512Bytes. Typically, it takes the Flash/EE memory controller 20msec to erase a page, and 50sec to write a 16-Bit word. These Flash/EE memory timings are independent of MCU core clock. 94kBytes of Flash/EE memory are available to the user as code and non-volatile data memory. There is no distinction between data and program, as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE memory are necessary for each instruction fetch. When operating at speeds less than 20.48MHz the Flash/EE memory controller can transparently fetch the second 16-bit half word (part of the 32-bit ARM op-code) within a single core clock period. It is therefore recommend that for speeds less than 20.48MHz, i.e. CD > 0, that ARM mode is used. For 20.48MHz operation, i.e. CD = 0 , it is recommended to operate in THUMB mode. The Flash/EE memory is physically located at 0x80000. Upon a hard reset it is logically mapped to 0x00000000. The factory default contents of all Flash/EE memory locations is 0xFF. Flash/EE memory may be read in 8/16/32 bit segments, and written in segments of 16 bits. The Flash/EE memory is rated for 10K endurance cycles. This rating is based on the number of times that each individual half word ( 16 bit location ) is cycled i.e. erased and programmed. A redundancy scheme may be implemented in software to ensure greater than 10K cycles endurance. The user may also write data variables to the Flash/EE memory during run-time code execution, e.g. for storing diagnostic
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Preliminary Technical Data
- FEExPRO (x= 0 or 1): A buffer of the FEEHIDE register, which is used to store the FEEHIDE value, so it is automatically downloaded to the FEEHIDE registers on subsequent reset and power-on events. NOTE: User Software must ensure that the Flash/EE memory controller has completed any Erase or Write cycle before the PLL is powered down. If the PLL is powered down before an Erase or Write cycle is
ADUC7032
completed, the Flash/EE page or byte may be corrupted. The following sections describe in detail the bit designations of each of Flash/EE control MMRs
FEE0CON and FEE1CON Registers :
Name : Address : Default Value (both registers) : Access : Function : FEE0CON and FEE1CON 0xFFFF0E08 and 0xFFFF0E88 0x07 Read/Write Access
These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for Block0 (32KB) and Block1 (64KB).
Table 11: Command Codes in FEE0CON and FEE1CON
Code 0x00* 0x01* 0x02* 0x03* 0x04* 0x05* 0x06*
Command Reserved Single Read Single Write Erase-Write Single Verify Single Erase Mass erase
Description (note x is 0 or 1 to designate Flash/EE Block 0 or 1) Reserved, this command should not be written by user code Load FEExDAT with the 16-bit data indexed by FEExADR Write FEExDAT at the address pointed by FEExADR. This operation takes 50s. Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20ms Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA bit 1 Erase the page indexed by FEExADR Erase Block0(30kByte) or Block1(64kByte) of user space. The 2kByte Kernel is protected. This operation takes 1.2s To prevent accidental execution, a command sequence is required to execute this instruction, this is described below. Default command. Reserved, this command should not be written by user code Reserved, this command should not be written by user code Reserved, this command should not be written by user code FEE0CON: This command will result in a 24-bit LFSR based signature been generated and loaded into FEE0SIG. If FEE0ADR is less than 0x97800, this command will result in a 24 bit LFSR based signature of the user code space from the page specified in FEE0ADR upwards, including the Kernel, security bits and Flash/EE key. If FEE0ADR is greater than 0x97800, the Kernel and manufacturing data is signed FEE1CON: This command will result in a 24-bit LFSR based signature been generated, beginning at FEE1ADR and ending at the end of the 63.5k Block, and loaded into FEE1SIG. The last page of this block is not included in the Sign generation. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key Reserved, this command should not be written by user code Reserved, this command should not be written by user code No operation, interrupt generated
0x07 0x08 0x09 0x0A 0x0B
Reserved Reserved Reserved Signature
0x0C 0x0D 0x0E 0x0F
*
Protect Reserved Reserved Ping
The FEExCON will always read 0x07 immediately after execution of any of these commands.
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Preliminary Technical Data
Command Sequence for executing a Mass Erase
Giving the significance of the `Mass Erase' command, a specific code sequence must be executed to initiate this operation. 1. 2. 3. 4. Set bit 3 in FEExMOD. Write 0xFFC3 in FEExADR Write 0x3CFF in FEExDAT Run the Mass Erase command 0x06 in FEExCON
ADUC7032
This sequence is illustrated in the following example,: FEExMOD= 0x08 FEExADR= 0xFFC3 FEExDAT= 0x3CFF FEExCON= 0x06; while (FEExSTA & 0x04){}
// Mass-Erase command //Wait for command to finish
Note: To run the mass erase command via FEE0CON, Write protection on the lower 64kbytes must be disabled, i.e. FEE1HIDE/FEE1PRO are set to 0xFFFFFFFF.. This may be done be first removing the protection or erasing the lower 64kbytes first.
FEE0STA and FEE1STA Registers :
Name : Address : Default Value (both registers) : Access : Function : FEE0STA and FEE1STA 0xFFFF0E00 and 0xFFFF0E80 0x00 ReadOnly
These 8-bit read only registers can be read by user code and reflect the current status of the Flash/EE memory controllers.
Table 12: FEE0STA and FEE1STA MMR bit designations
Bit 15-4 3
Description (note x is 0 or 1 to designate Flash/EE Block 0 or 1) Not Used These bits are not used and will always read as 0. Flash Interrupt Status Bit Set automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set Cleared automatically when the FEExSTA register is read by user code Flash/EE controller busy Set automatically when the Flash/EE controller is busy Cleared automatically when the controller is not busy Command fail Set automatically when a command written to FEExCON completes unsuccessfully Cleared automatically when the FEExSTA register is read by user code Command Successful Set automatically by MCU when a command is completed successfully. Cleared automatically when the FEExSTA register is read by user code
2
1
0
FEE0ADR and FEE1ADR Registers:
Name : Address : Default Value : Access : Function : FEE0ADR and FEE1ADR 0xFFFF0E10 and 0xFFFF0E90 Non Zero Read/Write Access This 16-bit register dictates the address upon which any Flash/EE command executed via FEExCON will act upon.
FEE0DAT and FEE1DAT Registers:
Name : Address : Default Value : Access : Function : FEE0DAT and FEE1DAT 0xFFFF0E0C and 0xFFFF0E8C Non Zero Read/Write Access This 16-bit register contains the data either read from or to be written to the Flash/EE memory.
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Preliminary Technical Data
FEE0MOD and FEE1MOD Registers :
Name : Address : Default Value (both registers) : Access : Function : FEE0MOD and FEE1MOD 0xFFFF0E04 and 0xFFFF0E84 0x00 Read/Write
ADUC7032
These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers.
Table 13: FEE0MOD and FEE1MOD MMR bit designations
Bit 15-7 6, 5 4
Description (note: x is 0 or 1 to designate Flash/EE Block 0 or 1) Not Used These bits are reserved for future functionality and should be written as 0 by user code Flash/EE Security Lock Bits These bits must be written as [6,5] = 1,0 to complete the Flash security protect sequence Flash/EE Controller Command Complete Interrupt Enable This bit is set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command. This bit is cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command. Flash/EE Erase/Write Enable Set by user code to enable the Flash/EE erase and write access via FEExCON Cleared by user code to disable the Flash/EE erase and write access via FEExCON Reserved and should be written as zero Flash/EE Controller Abort Enable This bit is set to 1 by user code to enable the Flash/EE controller abort functionality. Reserved and should be written as zero
3 2 1 0
FLASH/EE MEMORY SECURITY
The 94kByte of Flash/EE memory available to the user can be read and write protected using the FFE0HID and FEE1HID registers. In Block0, the FEE0HID MMR protects the 30kBytes. Bits 0-28 of this register protect pages 0-57 from writing. Each bit protects 2 pages, i.e. 1kBytes. Bits 29-30 protect pages 58 and 59 respectively, i.e. each bit write protects a single page of 512 bytes. The MSB of this register (Bit31) protects Block0 from been read via JTAG. The FEE0PRO register mirrors the bit definitions of the FEE0HID MMR. The FEE0PRO MMR allows user code to lock the protection or security configuration of the Flash memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. This flexibility allows the user to set and test protection settings temporarily using the FEE0HID MMR and subsequently lock the required protection configuration (using FEE0PRO) when shipping protection systems into the field. In Block1 (64K), the FEE1HID MMR protects the 64kBytes. Bits 0-29 of this register protect pages 0-119 from writing. Each bit protects 4 pages, i.e. 2kBytes. Bit30 protect pages 120-127, i.e. bit 30 write protects eight pages of 512 bytes. The MSB of this register (Bit31) protects Flash/EE Block1, from been read via JTAG. As with Block0, FEE1PRO register mirrors the bit definitions of the FEE1HID MMR. The FEE1PRO MMR is allows user code to lock the protection or security configuration of the Flash memory so that the protection configuration is automatically loaded on subsequent power-on or reset events.
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Preliminary Technical Data
Block0, Flash/EE Memory Protection Registers :
Name : Address : Default Value (both registers) : Access : Function : FEE0HID and FEE0PRO 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO) 0xFFFFFFFF Read/Write Access
ADUC7032
These registers are written by user code to configure the protection of the Flash/EE memory.
Table 14: FEE0HID and FEE0PRO MMR bit designations
Bit 31 30
Description (note: x is 0 or 1 to designate Flash/EE Block 0 or 1) Read protection Cleared by user to protect the 32kbyte Flash/EE Block code via JTAG read access Set by user to allow reading the 32kbyte Flash/EE Block code via JTAG read access Write Protection Bit This bit is set by user code to unprotect protect page 59 This bit is cleared by user code write protect page 59 Write Protection Bit This bit is set by user code to unprotect page 58 This bit is cleared by user code write protect page 58 Write Protection Bits When set by user code these bits will unprotect pages 0-57 of the 30KB Flash/EE code memory. Each bit write protects 2 pages and each pages consists of 512 bytes. When cleared by user code these bits will write protect pages 0-57 of the 30KB Flash/EE code memory. Each bit write protects 2 pages and each pages consists of 512 bytes.
29 28-0
Block1, Flash/EE Memory Protection Registers :
Name : Address : Default Value (both registers) : Access : Function : FEE1HID and FEE1PRO 0xFFFF0EA0 (for FEE0HID) and 0xFFFF0E9C (for FEE0PRO) 0xFFFFFFFF Read/Write Access
These registers are written by user code to configure the protection of the Flash/EE memory.
Table 15: FEE1HID and FEE1PRO MMR bit designations
Bit 31
Description Read protection Cleared by user to protect the 64kbyte Flash/EE Block code via JTAG read access Set by user to allow reading the 64kbyte Flash/EE Block code via JTAG read access Read protection When set by user code these bits will protect pages 120-127 of the 64KB Flash/EE code memory. This bit write protects 8 pages and each page consists of 512 bytes. When cleared by user code these bits will write protect pages 120-127 of the 64KB Flash/EE code memory.This bit write protects 8 pages and each page consists of 512 bytes. Write Protection Bits When set by user code these bits will unprotect pages 0-119 of the 64KB Flash/EE code memory. Each bit write protects 4 pages and each pages consists of 512 bytes. When cleared by user code these bits will write protect pages 0-119 of the 64KB Flash/EE code memory. Each bit write protects 2 pages and each pages consists of 512 bytes.
30
29-0
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Preliminary Technical Data
In Summary, there are three levels of protection: - Temporary Protection can be set and removed by writing directly into FEExHID MMR. This register is volatile and therefore protection will only be in place while the part remains powered on. This protection is not reloaded after a power cycle. - Keyed Permanent Protection can be set via FEExPRO which is used to lock the protection configuration. The software key used at the start of the required FEExPRO write sequence is saved once and MUST subsequently be used for any subsequent access of the FEExHID or FEExPRO MMRs. A mass erase will set the key back to 0xFFFF but will also erase the entire user code space. - Permanent Protection can be set via FEExPRO, similarily to Keyed Permanent Protection, the only difference been that the software key used is 0xDEADDEAD. Once the FEExPRO write sequence is saved, only a mass erase will set the key back to 0xFFFFFFFF. This will also erase the entire user code space.
ADUC7032
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as: 1. Initial page erase sequence. 2. Read/verify sequence a single Flash/EE. 3. Byte program sequence memory. 4. Second read/verify sequence endurance cycle. In reliability qualification, every half word (16-bit wide) location of the three pages(top, middle and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in Table 1, the parts' Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 . the results allow the specification of a minimum endurance figure over supply, temperature of 10,000 cycles. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts is qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 85C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. Also note that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ as shown in Figure 12.
Sequence to write the key and set permanent protection: 1. Write in FEExPRO corresponding to the pages to be protected. 2. Write the new (user defined) 32 bit key in FEExADR [ Bits 31-16 ] and FEExDAT [ Bits 15-0 ]. 3. Write 1,0 in FEExMOD[6:5] and set FEExMOD[3]. 4. Run the write key command 0x0C in FEExCON. To remove or modify the protection the same sequence can be used with a modified value of FEExPRO. The sequence above is illustrated in the following example, this protects writing pages 4 and 5of the FLASH: FEExPRO =0xFFFFFFFB; FEExADR =0x66BB; FEExDAT =0xAA55; FEExMOD = 0x0048 FEExCON = 0x0C; while (FEExSTA & 0x04){} //Protect pages 4 and 5 //32 bit key value [Bits 31-16] //32 bit key value [Bits 15-0] // Lock Security Sequence // Write key command //Wait for command to finish
600
RETENTION (Years)
450
300
150
04955-085
0
30
40
55 70 85 100 125 JUNCTION TEMPERATURE (C)
135
150
Figure 12. Flash/EE Memory Data Retention
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Preliminary Technical Data
CODE EXECUTION TIME FROM SRAM AND FLASH/EE
This chapter describes SRAM and Flash/EE access times during execution for applications where execution time is critical.
ADUC7032
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM is 2ns and a clock cycle is 49ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM, or three cycle if the data is in Flash/EE, one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, for example a branch instruction will take one cycle to fetch but also two cycle to fill the pipeline with the new instructions.
an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instruction are more complex and are summarized Table 16.
Table 16: Typical execution cycles in ARM/Thumb mode
Instructions LD LDH LDM/POP STR STRH STM/PUSH
Fetch cycles 2/1 2/1 2/1 2/1 2/1 2/1
Dead time 1 1 N 1 1 N
Data access 2 1 2xN 2 x 50s 50s 2 x N x 50s
Execution from Flash/EE
Because the Flash/EE width is 16-bit, execution from Flash/EE cannot be done in one cycle, as from SRAM, when CD bit =0. Also some dead time is needed before accessing data for any value of CD bits. In ARM mode, where instructions are 32 bits, two extra cycles are needed to fetch any instruction when CD = 0 and in Thumb mode, where instructions are 16 bits, one extra cycle is needed to fetch any instruction. Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipe-line. A data processing instruction involving only core register doesn't require any extra clock cycle but if it involves data in Flash/EE,
With 1Rev. PrD | Page 37 of 128
Preliminary Technical Data
ADUC7032 KERNEL
The ADUC7032 features an on-chip Kernel resident in the top 2k of the Flash/EE Code space. After any reset event, this kernel copies the factory calibrated data from the manufacturing data space, into the various on-chip peripherals. The peripherals calibrated by the Kernel are: PSM Power Supply Monitor Precision, Oscillator Low Power, Oscillator REG_AVDD/ REG_DVDD Low Power Voltage Reference Normal Mode Voltage Reference Current ADC ( Offset and Gain ) Voltage ADC ( Offset and Gain ) Temperature ADC ( Offset and Gain )
ADUC7032
The ADUC7032 also features an On-Chip LIN downloader. The operation of this download is detailed in "ADUC7032Series Flash/EE Programming via LIN" Technote. A flow chart showing the execution of the kernel is shown in Figure 13. The current revision of the Kernel may be derived from SYSSER1, as described in Table 85. For the duration of Kernel execution, the Watchdog Timer is active with a timeout period of 30ms. This ensures that if an error occurs in the Kernel, the ADUC7032 will be reset. After any reset, the Watchdog timer is disabled once the Kernel code is exited. Normal Kernel execution time, excluding LIN Download, is approximately 5ms. It is only possible to leave LIN download mode via a Reset. SRAM is not corrupted during normal Kernel execution. SRAM is corrupted during LIN download Kernel execution. NOTE: User code will not be executed unless location 0x14 contains either 0x27011970 or the checksum of Page Zero, excluding location 0x14. If location 0x14 does not contain this information user code will not be executed and LIN download mode will be entered. For more information please refer to the relevant LIN download Technote.
User MMRs which may be modified by the kernel and differ from their POR default values are as follows: R0-R15 GP0CON/GP2CON SYSCHK ADCMDE/ADC0CON FEE0ADR/FEE0CON/FEESIG HVDAT/HVCON HVCFG0/1 T3LD
Rev. PrD | Page 38 of 128
Preliminary Technical Data
INITIALIZE ON-CHIP PERIPHERALS TO FACTORY CALIBRATED STATE
ADUC7032
NO
JTAG MODE? NTRST = 1
YES
PAGE ERASED? 0x14 = 0xffffffff
NO
KEY PRESENT? 0x14 = 0x27011970
YES
NO YES
CHECKSUM PRESENT? 0x14 = CHECKSUM
EXECUTE USER CODE
NO
FLAG PAGE 0 ERROR
NO
LIN COMMAND
YES
RESET COMMAND
05994-013
Figure 13: ADUC7032 Kernel Flowchart
Rev. PrD | Page 39 of 128
Preliminary Technical Data
MEMORY MAPPED REGISTERS
The Memory Mapped Register (MMR) space is mapped into the top 4kBytes of the MCU memory space and accessed by indirect addressing, load and store commands, through the ARM7 banked registers. An outline of the ADUC7032s Memory Mapped Register Bank is shown in Figure 14. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the ARM7 core registers (described in ARM Registers) reside in the MMR area. As can be seen from the detailed MMR map in Table 17, the MMR data widths vary from 1 Byte (8 bits) to 4 Bytes (32 bits). The ARM7 core can access any of the MMRs (single byte or multiple byte width registers) with a 32 bit read or write access. The resultant read for example, aligned per `little endian' format described earlier. However, errors will result if the ARM7 core tries to access 4 Byte (32 bit) MMRs with a 16-bit access. In the case of a (16-bit) write access to a 32-bit MMR, the (upper) 16 most significant bits will be written as 0's. More obviously, in the case of a 16-bit read access to a 32-bit MMR, only 16 of the MMR bits can be read.
0xFFFFFFFF 0xFFFF1000 0xFFFF0E00 0xFFFF0D50 0xFFFF0D00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0894 0xFFFF0880 0xFFFF0810 HV INTERFACE 0xFFFF0800 0xFFFF079C 0xFFFF0780 0xFFFF0730 UART 0xFFFF0700 0xFFFF0568 ADC 0xFFFF0500 0xFFFF044C 0xFFFF0400 0xFFFF0394 0xFFFF0380 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0318 0xFFFF0300 0xFFFF0244 0xFFFF0220 0xFFFF0110 0xFFFF0000 INTERRUPT CONTROLLER REMAP AND SYSTEM CONTROL PLL AND OSCILLATOR CONTROL GENERAL PURPOSE TIMER 4 LIN/BSD HARDWARE SERIAL TEST INTERFACE FLASH CONTROL INTERFACE
ADUC7032
GPIO
WATCHDOG TIMER 3
WAKE UP TIMER 2
GENERAL PURPOSE TIMER 1
TIMER 0
Figure 14: Top Level MMR Map
Rev. PrD | Page 40 of 128
05994-014
Preliminary Technical Data
Table 17 : Complete MMR List
ADUC7032
Address
Name
Byte
Access Type
Default Value
Page
Description
IRQ address base = 0xFFFF0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C IRQSTA IRQSIG1 IRQEN IRQCLR SWICFG FIQSTA FIQSIG
1
4 4 4 4 4 4 4 4 4
R R RW W W R R RW W
0x00000000
75 75
Active IRQ Source Current State of all IRQ sources ( Enabled and Disabled ) Enabled IRQ sources MMR used to disabled IRQ Sources Software Interrupt Configuration MMR Active IRQ Source Current State of all IRQ sources ( Enabled and Disabled ) Enabled IRQ sources MMR used to disabled IRQ Sources
0x00000000 0x00000000
75 75 76
0x00000000
75 75
FIQEN FIQCLR
0x00000000 0x00000000
75 75
System Control address base = 0xFFFF0200 0x0220 SYSMAP0 1 RW 0x0230 0x0234 0x0238 0x023C 0x0240 RSTSTA RSTCLR SYSSER02 SYSSER12 SYSCHK2 1 1 4 4 4 RW W RW RW RW 0x01 0x00
29 30 30 125 126 126
REMAP control Register Reset Status MMR RSTSTA clear MMR SYSTEM Serial Number 0 SYSTEM Serial Number 1 Kernel Checksum Timer 0 Load Register Timer 0 Value Register 0 Timer 0 Value Register 1 Timer 0 Control MMR Timer 0 Interrupt Clear Register Timer 0 Capture Register Timer 1 Load Register Timer 1 Value Register Timer 1 Control MMR Timer 1 Interrupt Clear Register Timer 1 Capture Register Timer 2 Load Register Timer 2 Value Register Timer 2 Control MMR Timer 2 Interrupt Clear Register Timer 3 Load Register Timer 3 Value Register
Timer address base = 0xFFFF0300 0x0300 T0LD 4 RW 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 T0VAL0 T0VAL1 T0CON T0CLRI T0CAP T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD2 T3VAL
2
0x00000000 0x0000 0x00000000 0x0000 0xFF 0x0000 0x00000000 0xFFFFFFFF 0x0000 0xFF 0x00000000 0x00000000 0xFFFFFFFF 0x00 0xFF
79 78 78 79 79 78 80 80 81 80 81 82 82 83 82 84 84
2 4 2 1 2 4 4 2 1 4 4 4 2 1 2 2
R R RW W RW RW R RW W RW RW R RW W RW R
Rev. PrD | Page 41 of 128
Preliminary Technical Data
0x0368 0x036C T3CON2 T3CLRI2 2 1 RW W 85 85 0x02 0x79 69 70 71 70 70 0x00 0x08 0x00 0x00 0x00 0x00 0x0000 0x00 0x00 0x0000 0x0000 0x0000 0x0007 0x00 0x0000 0x0000 0x0000 70 70 73 73 74 74 74 49 50 51 52 53 54 55 57 58 58 58 58 58 58 58 59 59 59 0x0001 0x0000 0x0000 59 59 59 Timer 3 Control MMR Timer 3 Interrupt Clear Register PLL Status MMR POWCON Pre Write Key
ADUC7032
PLL base address = 0xFFFF0400 0X0400 PLLSTA 4 RW 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 0x042C 0x0440 0x0444 0x0448 0x044C POWKEY0 POWCON POWKEY1 PLLKEY0 PLLCON PLLKEY1 OSC0TRM OSC0CON OSC0STA 0SC0VAL0 OSC0VAL1 4 1 4 4 1 4 1 1 1 2 2 W RW W W RW W RW RW R R R
Power Control and Core speed Control Register POWCON Post Write Key PLLCON Pre Write Key PLL clock source selection MMR PLLCON Post Write Key Low Power Oscillator trim bits MMR. Low Power Oscillator Calibration Control MMR Low Power Oscillator Calibration Status MMR Low Power Oscillator Calibration Counter 0 MMR Low Power Oscillator Calibration Counter 1 MMR ADC Status MMR ADC Interrupt Source Enable MMR ADC Mode Register Current ADC Control MMR Voltage ADC Control MMR Temperature ADC Control MMR ADC Filter Control MMR ADC Configuration MMR Current ADC Result MMR V ADC Result MMR V ADC Result MMR Current/Voltage Result FIFO Current ADC Offset MMR Voltage ADC Offset MMR Temperature ADC Offset MMR Current ADC Gain MMR Voltage ADC Gain MMR Temperature ADC Gain MMR Current ADC Result Count Limit Current ADC Result Count Value Current ADC Result Threshold
ADC address base = 0xFFFF0500 0x0500 ADCSTA 2 R 0x0504 0x0508 0x050C 0x0510 0x0514 0x0518 0x051C 0x0520 0x0524 0x0528 0x052C 0x0530 0x0534 0x0538 0x053C 0x0540 0x0544 0x0548 0x054C 0x0550 ADCMSKI ADCMDE ADC0CON ADC1CON ADC2CON ADCFLT ADCCFG ADC0DAT ADC1DAT ADC2DAT ADCFIFO ADC0OF ADC1OF ADC2OF
2
1 1 2 2 2 2 1 2 2 2 4 2 2 2 2 2 2 2 2 2
RW RW RW RW RW RW RW R R R R RW RW RW RW RW RW RW R RW
2
2
ADC0GN2 ADC1GN ADC2GN
2 2
ADC0RCL ADC0RCV ADC0TH
Rev. PrD | Page 42 of 128
Preliminary Technical Data
0x0554 0x0558 0x055C 0x0560 0x057C ADC0TCL ADC0THV ADC0ACC ADC0ATH ADCREF
2
ADUC7032
0x01 0x00 0x00000000 0x00000000 59 60 60 60 60 Current ADC Result Threshold Count Limit Current ADC Result Threshold Count Limit Value Current ADC Result Accumulator Current ADC Result Accumulator Threshold Low Power Mode Voltage Reference Scaling Factor
1 1 4 4 4
RW R R RW R
UART BASE ADDRESS = 0XFFFF0700 0x0700 COMTX 1 W COMRX COMDIV0 0x0704 0x0708 0x070C 0x0710 0x0714 0X072C COMIEN0 COMDIV1 COMIID0 COMCON0 COMCON1 COMSTA0 COMDIV2 1 1 1 1 1 1 1 1 2 R RW RW R/W R RW RW R RW
0x00
107 107 107
UART Transmit Register UART Receive Register UART Standard Baud Rate Generator Divisor Value 0 UART Interrupt Enable MMR 0 UART Standard Baud Rate Generator Divisor Value 1 UART Interrupt Identification 0 UART Control Register 0 UART Control Register 1 UART Status Register 0 UART Fractional Divider MMR LHS Status MMR LHS Control MMR 0 LHS Timer 0 MMR LHS Control MMR 1 LHS Timer 1 MMR
0x00 0x01 0x00 0x00 0x60 0x0000
110 107 110 108 109 109 111 116 117 118 118 119 99 99
LIN Hardware Sync base address = 0XFFFF0780 0x0780 LHSSTA 1 R 0x00 0x0784 0x0788 0x078C 0x0790 LHSCON0 LHSVAL0 LHSCON1 LHSVAL1 2 2 1 1.5 R/W R/W R/W R/W 0x0000 0x0000 0x32 0x0000
High Voltage Interface base address = 0xFFFF0800 0x0804 HVCON 1 RW 0x080C HVDAT 1.5 RW
High Voltage Interface Control MMR High Voltage Interface Data MMR SPI Status MMR SPI Receive MMR SPI Transmit MMR SPI Baud Rate Select MMR SPI Control MMR GPIO Port 0 Control MMR GPIO Port 1 Control MMR GPIO Port 2 Control MMR GPIO Port 0 Data Control MMR GPIO Port 0 Data Set MMR GPIO Port 0 Data Clear MMR GPIO Port 1 Data Control MMR GPIO Port 1 Data Set MMR
SPI base address = 0xFFFF0A00 0x0A00 SPISTA 1 R 0x0A04 0x0A08 0x0A0C 0x0A10 SPIRX SPITX SPIDIV SPICON 1 1 1 2 R W RW RW
0x00 0x00 0x00 0x1B 0x00 0x00000000 0x00000000 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX
114 114 114 114 113 88 89 89 90 93 95 91 94
GPIO base address = 0xFFFF0D00 0x0D 00 GP0CON 4 RW 0x0D 04 0x0D 08 0x0D 20 0x0D 24 0x0D 28 0x0D 30 0x0D 34 GP1CON GP2CON GP0DAT3 GP0SET3 GP0CLR3 GP1DAT3 GP1SET3 4 4 4 4 4 4 4 RW RW RW W W RW W
Rev. PrD | Page 43 of 128
Preliminary Technical Data
0x0D 38 0x0D 40 0x0D 44 0x0D 48 GP1CLR3 GP2DAT3 GP2SET3 GP2CLR3 4 4 4 4 W W W W 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x00 0x00 0x07 95 92 94 96 33 34 32 33 33 0xFFFFFF 0x00000000 0xFFFFFFFF 0x00 0x00 0x07 35 35 33 34 32 33 33 0x0000 0x00000000 0xFFFFFFFF 35 35 GPIO Port 1 Data Clear MMR GPIO Port 2 Data Control MMR GPIO Port 2 Data Set MMR GPIO Port 2 Data Clear MMR Flash/EE Status MMR Flash/EE Control MMR Flash/EE Control MMR Flash/EE Data MMR Flash/EE Address MMR Flash/EE LFSR MMR Flash/EE Protection MMR Flash/EE Protection MMR Flash/EE Status MMR Flash/EE Control MMR Flash/EE Control MMR Flash/EE Data MMR Flash/EE Address MMR Flash/EE LFSR MMR Flash/EE Protection MMR Flash/EE Protection MMR
ADUC7032
Flash/EE base address = 0xFFFF0E00 0x0E00 FEE0STA 1 R 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 0x0E80 0x0E84 0x0E88 0x0E8C 0x0E90 0x0E98 0x0E9C 0x0EA0
1 2 3
FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SIG FEE0PRO FEE0HID FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SIG FEE1PRO FEE1HID
2 1 2 2 3 4 4 1 2 1 2 2 3 4 4
RW RW RW RW R RW RW R RW RW RW RW R RW RW
Depends on the level on the external interrupt pins GP0, GP5, GP7 and GP8 Updated by Kernel Depends on the level on the external GPIO pins
Rev. PrD | Page 44 of 128
Preliminary Technical Data
16-BIT - ANALOG TO DIGITAL CONVERTERS
The ADUC7032 incorporates three independent sigma-delta ADCs namely, the Current Channel ADC (I-ADC), the Voltage Channel ADC (V-ADC) and the Temperature Channel ADC (T-ADC). These precision measurement channels integrate onchip buffering, programmable gain amplifier, 16-bit sigmadelta modulators and digital filtering and are intended for the precision measurement of current, voltage and temperature variables in 12V automotive battery systems.
ADUC7032
the digital information. A modified Sinc3 programmable lowpass filter is then employed to decimate the modulator output data stream to give a valid 16-Bit data conversion result at programmable output rates from 4Hz to 8 KHz in Normal mode and 1Hz to 2kHz in Low Power Mode. The I-ADC also incorporates counter, comparator and accumulator logic. This allows the I-ADC result to generate an interrupt after a predefined number of conversions have elapsed or if the I-ADC result exceeds a programmable threshold value. A fast ADC-Over-Range feature is also supported. Once enabled, a 32-bit accumulator automatically sums the 16-bit I-ADC results. The time to a first valid (fully settled) result on the current channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on.
CURRENT CHANNEL ADC (I-ADC)
This ADC is intended to convert battery current sensed through an external 100 shunt resistor. On-Chip programmable gain mean the I-ADC can be configured to accommodate battery current levels from 1A to 1500A As shown in Figure 15 below, the I-ADC employs a sigma-delta conversion technique to realize 16 bits of no missing codes performance. The sigma-delta modulator converts the sampled input signal into a digital pulse train whose duty cycle contains
ANALOG INPUT Diagnostic Current Sources ANALOG INPUT PROGRAMMABLE CHOPPING
THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE.
SIGMA-DELTA MODULATOR
THE MODULATOR PROVIDES A HIGH FREQUENCY 1-BIT DATA STREAM (THE OUTPUT OF WHICH IS ALSO CHOPPED) TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE.
Two 50uA IIN+ and IINCurrent Sources
SIGMA-DELTA ADC
THE SIGMA-DELTA ARCHITECTURE ENSURES 16 BITS NO MISSING CODES.
PROGRAMMABLE GAIN AMPLIFIER
THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS EIGHT BIPOLAR INPUT RANGES FROM 2.3mV TO 1.2V (INT V REF = 1.2V).
REG_AVDD REG_AVDD
OUTPUT AVERAGE
AS PART OF THE CHOPPING IMPLEMENTATION, EACH DATA-WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR
ADC FAST OVER-RANGE
GENERATES AN ADC INTERRUPT IF THE CURRENT INPUT IS GROSSLY OVER-RANGED
IN+ IN-
SIGMA-DELTA A/D CONVERTER SIGMADELTA MODULATOR PROGRAMMABLE DIGITAL FILTER CHOP OUTPUT AVERAGE
PGA
VREF/ 136 GND CHOP
BUF
+
ANALOG INPUT Diagnostic Voltage Source BUFFER AMPLIFIER
THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE PGA DRIVING THE SIGMA_DELTA MODULATOR.
ADC ACCUMULATOR
ACCUMULATES THE ADC RESULT
INTERNAL REFERNCE
OFFSET COEFFICIENT
x
OUTPUT FORMAT
VREF/136 Voltage Input
GAIN COEFFICIENT
ADC RESULT ACCUMULATOR
ADC INTERRUPT GENERATOR
GENERATES AN ADC RESULT FROM ANY ONE OF FOUR SOURCES
PRECISION REFERENCE
THE INTERNAL 5PPM/C REFERNCE IS ROUTED TO THE ADC BY DEFAULT. AN EXTERNAL REFRENCEON THE VREF PIN CAN ALSO BE SELECTED
VREF
ADC RESULT
OUTPUT SCALING
THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT.
ADC RESULT
ADC RESULT COUNTER
ADC INTERRUPT
PROGRAMMABLE DIGITAL FILTER
THE SINC 3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR. THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE ADCFLT MMR
ADC THRESHOLD DIGITAL COMPARATOR
THE ADC RESULT IS COMPARED TO A PRESET THRESHOLD
THRESHOLD COUNTER ADC RESULT COUNTER
COUNTS ADC RESULTS, GENERATES AN INTERRUPT ON COUNTER OVERFLOW
THRESHOLD COUNTER
COUNTS UP IF ADC RESULT>THRESHOLD COUNTS DOWN/RESET IF ADC RESULTFigure 15: Current ADC, Top Level Overview
Rev. PrD | Page 45 of 128
Preliminary Technical Data
VOLTAGE CHANNEL ADC (V-ADC)
This ADC is intended to convert battery voltage As with the Current Channel ADC described previously, this ADC employs an identical sigma-delta conversion technique, including a modified Sinc3 low-pass filter to give a valid 16-Bit data conversion result at programmable output rates from 4Hz to 8 KHz. An external RC filter network is not required as this is implemented internally in the voltage channel. The external battery voltage (VBAT) is routed to the ADC input via an on-chip high voltage, resistive attenuator This must be enabled/disabled via HVCFG1[7]. The time to a first valid (fully settled) result on the voltage channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on. This ADC is again buffered but unlike the current channel has a fixed VBAT input range of 0 V to 28.8V (assuming an internal 1.2V reference). A top level overview of this ADC signal chain is shown in Figure 16 below.
ADUC7032
TEMPERATURE CHANNEL ADC (T-ADC)
This ADC is intended to convert battery temperature. The battery temperature can be derived via the on-chip temperature sensor or an external temperature sensor input. The time to a first valid (fully settled) result after an input channel switch on the temperature channel is three ADC conversion cycles with chop mode turned off and two ADC conversion cycles with chop mode turned on. As with the Current and Voltage Channel ADCs, this ADC employs an identical sigma-delta conversion technique, including a modified Sinc3 low-pass filter to give a valid 16-Bit data conversion result at programmable output rates from 4Hz to 8 KHz
SIGMA-DELTA MODULATOR ANALOG INPUT PROGRAMMABLE CHOPPING
THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE. THE MODULATOR PROVIDES A HIGH FREQUENCY 1-BIT DATA STREAM (THE OUTPUT OF WHICH IS ALSO CHOPPED) TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE.
SIGMA-DELTA ADC
THE SIGMA-DELTA ARCHITECTURE ENSURES 16 BITS NO MISSING CODES.
DIFFERENTIAL ATTENUATOR
DIVIDE BY 24, INPUT ATTENUATOR
OUTPUT AVERAGE
AS PART OF THE CHOPPING IMPLEMENTATION, EACH DATA-WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR
VBAT 45R 2R 1R CHOP
SIGMA-DELTA A/D CONVERTER SIGMADELTA MODULATOR PROGRAMMABLE DIGITAL FILTER CHOP OUTPUT AVERAGE
BUF
+
BUFFER AMPLIFIER
THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUT.
INTERNAL REFERNCE
OFFSET COEFFICIENT
x
OUTPUT FORMAT
GAIN COEFFICIENT
PRECISION REFERENCE
THE INTERNAL 5PPM/C REFERNCE IS ROUTED TO THE ADC BY DEFAULT. AN EXTERNAL REFRENCEON THE VREF PIN CAN ALSO BE SELECTED
VREF
OUTPUT SCALING
THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT.
ADC RESULT
PROGRAMMABLE DIGITAL FILTER
THE SINC 3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR. THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE ADCFLT MMR
ADC RESULT
FINAL (16-BIT) ADC RESULT
Figure 16 : Voltage/ Temperature ADC, Top Level Overview
Rev. PrD | Page 46 of 128
Preliminary Technical Data
ADC GROUND SWITCH
The ADUC7032 features an integrated ground switch pin, GND_SW located on Pin15. This switch allows the user to dynamically disconnect ground from external devices. It allows either a direct connection to ground, or a connection to ground via a 20k, this additional resistor may be used to reduce the number of external components required for an NTC circuit. The ground switch feature may be used for reducing power consumption on application specific boards.. An example application is shown in Figure 17. This diagram shows an external NTC used in two modes, one using the internal 20k resistor, and the second showing a direct connection to ground, via the GND_SW. ADCCFG[7] controls the connection of the ground switch to ground and ADCMDE[6] controls the GND_SW resistance.
ADUC7032
The possible combinations are shown in Table 18.
Table 18 : GND_SW Configuration
ADCCFG[7]
0 0 1 1
ADCMDE[6]
0 1 0 1
GND_SW
Floating Floating Direct connection to Ground Connected to ground via 20k resistor
REG_AVDD RREF VTEMP NTC
REG_AVDD VTEMP
GND_SW ADCCFG[7]
NTC
20k
05994-017
ADCMDE[6]
05994-018
20k
Figure 17 : Example External Temperature Sensor Circuits
Figure 18: Internal Ground Switch Configuration
Rev. PrD | Page 47 of 128
Preliminary Technical Data
ADC NOISE PERFORMANCE TABLES
ADUC7032
Table 19, Table 20 and Table 21 below show the output RMS noise in V for some typical output update rates on the I and V/T ADCs. The numbers are typical and are generated at a differential input voltage of 0 V The output RMS noise is specified as the standard deviation (or 1 X Sigma) of the distribution of ADC output codes collected when the ADC input voltage is at a dc voltage. It is expressed as V RMS.
Table 19 : Current Channel ADC, Normal Power Mode, Typical Output RMS Noise (V)
ADCFLT
Data Update Rate
4Hz 10Hz 50Hz 1KHz 8KHz
ADC Input Range 2.3mV (512)
0.040 0.060 0.142 0.620 2.000
4.6mV (256)
0.040 0.060 0.142 0.620 2.000
4.68mV (128)
0.043 0.060 0.144 0.625 2.000
18.75mV (64)
0.087 0.087 0.145 0.625 2.000
37.5mV (32)
0.087 0.087 0.170 0.770 2.650
75mV (16)
0.175 0.175 0.305 1.310 4.960
150mV (8)
0.35 0.35 0.380 1.650 8.020
300mV (4*)
0.7 0.7 0.7 2.520 15.0
600mV (2*)
2.8 2.8 2.8 7.600 55.0
1.2V (1*)
2.8 2.8 2.8 7.600 55.0
0xBF1D 0x961F 0x007F 0x0007 0x0000
*Please note that the maximum absolute input voltage allowed is -200mV to 300mV relative to ground
Table 20 : Voltage Channel ADC, Typical Output RMS Noise (referred to ADC Voltage attenuator Input)(V)
ADCFLT
Data Update Rate
4Hz 10Hz 1KHz 8KHz
28.8V ADC Input Range
65 65 180 1600
0xBF1D 0x961F 0x0007 0x0000
Table 21 : Temperature Channel ADC, Typical Output RMS Noise (V)
ADCFLT
Data Update Rate
4Hz 10Hz 1KHz 8KHz
0-1.2V ADC Input Range
2.8 2.8 7.5 55
0xBF1D 0x961F 0x0007 0x0000
Rev. PrD | Page 48 of 128
Preliminary Technical Data
ADC MMR INTERFACE
The ADC is controlled and configured via a number of MMRs that are described in detail in the following pages:
ADUC7032
ADC Status Register :
Name : Address : Default Value : Access : Function : ADCSTA 0xFFFF0500 0x0000 Read Only This read only register holds general status information related to the mode of operation or current status of the ADUC7032ADCs.
Table 22 : ADCSTA MMR Bit Designations
Bit 15
Description ADC Calibration Status This bit is set automatically in hardware to indicate an ADC calibration cycle has been completed. This bit is cleared after ADCMDE is written to.
14
ADC Temperature Conversion Error This bit is set automatically in hardware to indicate that a temperature conversion over-range or under-range has occurred. The conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. This bit will be cleared when a valid (in-range) temperature conversion result is written to the ADC2DAT register.
13
ADC Voltage Conversion Error This bit is set automatically in hardware to indicate that a voltage conversion over-range or under-range has occurred. The conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. This bit will be cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
12
ADC Current Conversion Error This bit is set automatically in hardware to indicate that an a current conversion over-range or under-range has occurred. The conversion result will be clamped to negative full-scale (under-range error) or positive full-scale (over-range error) in this case. This bit will be cleared when a valid (in-range) current conversion result is written to the ADC0DAT register.
11 10 9
Not Used This bit is reserved for future functionality and should not be monitored by user code Not Used This bit is reserved for future functionality and should not be monitored by user code ADCFIFO Error Flag This bit is set to 1 automatically to indicate that the FIFO has overflowed. This bit does not cause an interrupt but is latched high and can only be cleared by disabling the FIFO or reconfiguring the ADC. This bit will read 0 is the FIFO is disabled or if the FIFO has not overflowed.
8
ADC FIFO Empty Flag This bit is set to 1 automatically to indicate the ADC FIFO is empty. It is a flag bit only and cannot generate an interrupt. This bit reads 0 if the ADC FIFO is disabled.
7
ADC FIFO Full Flag This bit is set to 1 automatically to indicate the ADC FIFO is full and any subsequent I and V ADC conversion results will overflow and corrupt the ADC FIFO. This bit is cleared by disabling the FIFO or reconfiguring the ADC.
6
Accumulator Comparator Threshold Exceeded This bit indicates that the absolute value of the Current Channel Accumulator has exceeded the programmed threshold. This bit is cleared by disabling the Accumulator Comparator function in ADCCFG[6,5] or by reconfiguring the ADC.
5
Not Used This bit is reserved for future functionality and should not be monitored by user code
Rev. PrD | Page 49 of 128
Preliminary Technical Data
4 Current Channel ADC Comparator Threshold
ADUC7032
This bit is only valid if the Current Channel ADC comparator is enabled via the ADCCFG MMR. This bit is set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR. If the ADC threshold counter is used (ADC0TCL), this bit is only set once the specified number of I-ADC conversions equals the value in the ADC0THV MMR. 3 Current Channel ADC Over-Range Bit If the Over-Range Detect function is enabled via the ADCCFG MMR, this bit is set by hardware if the I-ADC input is grossly (>30% approx.) over-ranged. This bit is updated every 125usecs. Once set, this bit can only be cleared by software when
ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR.
2 Temperature Conversion Result Ready Bit If the Temperature Channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is written in the temperature data register (ADC2DAT MMR) This bit is cleared by reading either ADC2DAT or ADC0DAT. 1 Voltage Conversion Result Ready Bit If the Voltage Channel ADC is enabled, this bit is set by hardware as soon as a valid voltage conversion result is written in the voltage data register (ADC1DAT MMR) This bit is cleared by reading either ADC1DAT or ADC0DAT. 0 Current Conversion Result Ready Bit If the Current Channel ADC is enabled, this bit is set by hardware as soon as a valid current conversion result is written in the current data register (ADC0DAT MMR) This bit is cleared by reading ADC0DAT. NOTES 1. 2. 3. 4. 5. 6. 7. All bits defined in the top 8 MSBs (bits 8-15) of the MMR are used as flags only and will not generate interrupts All bits defined in the lower 8 LSBs (bits 0-7) of this MMR are logic OR'ed to produce a single ADC interrupt to the MCU core. In response to an ADC interrupt, user code should interrogate the ADCSTA MMR to determine the source of the interrupt. Each ADC interrupt source can be individually masked via the ADCMSKI MMR described below All ADC Result Ready bits are cleared by a read of the ADC0DAT MMR. If the Current Channel ADC is not enabled, all ADC Result Ready bits are cleared by a read of the ADC1DAT or ADC2DAT MMRs. To ensure that I-ADC, V-ADC and T-ADC conversion data are synchronous, user code should first read the ADC2DAT/ADC1DAT MMRs and then ADC0DAT MMR. New ADC conversion results will not be written to the ADCxDAT MMRs unless the respective ADC Result Ready bits are first cleared. The only exception to this rule is data conversion result updates when the ARM core is powered down. In this modes ADCxDAT registers will always contain the most recent ADC conversion result even though the Ready bits have not been cleared.
ADC Interrupt Mask Register :
Name : Address : Default Value : Access : Function : ADCMSKI 0xFFFF0504 0x00 Read/Write This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the same as the lower 8-bits in the ADCSTA MMR. If a bit is set by user code to a `1', the respective interrupt is enabled. By default all bits are `0' meaning all ADC interrupt sources are disabled.
Rev. PrD | Page 50 of 128
Preliminary Technical Data
ADC Mode Register :
Name : Address : Default Value : Access : Function : Bit 7 6 ADCMDE 0xFFFF0508 0x00 Read/Write
ADUC7032
The ADC Mode MMR is an 8-bit register that configures the mode .of operation of the ADC sub-system
Table 23 : ADCMDE MMR Bit Designations
Description Not Used This bit is reserved for future functionality and be written as 0 by user code 20K resistor select: This bit is set to 1 to select the 20 K resistor as shown in Figure 18 This bit is set to 0 to select the direct path to ground as shown in Figure 18 ( Default ).
5
Low Power Mode Reference Select: This bit is set to 1 to enable the Precision Voltage Reference in ADC Low Power Mode. This will increase current consumption. This bit is set to 0 to enable the Low Power Voltage Reference in ADC Low Power Mode ( Default ).
4-3
ADC Power Mode Configuration 0, 0 0, 1 ADC Normal Mode If enabled, the ADC will operate with normal current consumption yielding optimum electrical performance ADC Low Power Mode If enabled, the I-ADC will operate with reduced current consumption. This limitation is current consumption is achieved, (at the expense of ADC noise performance) by fixing the gain to 128 and using the on-chip low power (131kHz) oscillator to drive the ADC circuits directly. ADC Low Power-Plus Mode If enabled, the ADC will again operate with reduced current consumption. In this mode the gain is fixed to 512 and the current consumed is 200uA (approx.) more than ADC low Power Mode above. The additional current consumed also ensures ADC noise performance is better than that achieved in ADC Low Power Mode. Not Defined
1, 0
1, 1 2-0
ADC Operation Mode Configuration 0, 0, 0 ADC Power-Down Mode All ADC circuits (including internal reference) are powered-down 0, 0, 1 ADC Continuous Conversion Mode In this mode, any enabled ADC will continuously convert. 0, 1, 0 ADC Single Conversion Mode In this mode, any enabled ADC will perform a single conversion. The ADC will enter Idle Mode once the single shot conversion is complete. A single conversion will take 2/3 ADC clock cycles depending on the CHOP mode. 0, 1, 1 ADC IDLE Mode In this Mode, the ADC is fully powered on but is held in RESET 1, 0, 0 ADC Self-Offset Calibration In this mode, an offset calibration is performed on any enabled ADC using an internally generated 0V. The calibration is carried out at the user programmed ADC settings, therefore, as with a normal single ADC conversion, it will take 2/3 ADC conversion cycles before a fully settled calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to IDLE Mode and the Calibration and Conversion Ready status bits are set at the end of an offset calibration cycle. 1, 0, 1 ADC Self Gain Calibration In this mode, a gain calibration against an internal reference voltage is performed on all enabled ADCs. A gain calibration is a 2 stage process and takes twice the time of an offset calibration. The calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to IDLE Mode and the calibration and Conversion Ready status bits are set at the end of an gain calibration cycle. An ADC self gain calibration should only be carried out on the Current Channel ADC while pre-programmed, factory calibration coefficients (downloaded automatically from internal Flash) should be used for voltage temperature measurements. If an external NTC is used, an ADC Self Calibration should be done on the temperature channel.
Rev. PrD | Page 51 of 128
Preliminary Technical Data
ADUC7032
1, 1, 0 ADC System Zero-Scale Calibration In this mode, an zero-scale calibration is performed on enabled ADC channels against an external zero-scale voltage driven at the ADC input pins. The calibration is carried out at the user programmed ADC settings, therefore, as with a normal single ADC conversion, it will take 3 ADC conversion cycles before a fully settled calibration result is ready. 1, 1, 1 ADC System Full-Scale Calibration In this mode, an full-scale calibration is performed on enabled ADC channels against an external full-scale voltage driven at the ADC input pins.
Current Channel ADC Control Register :
Name : Address : Default Value : Access : Function : Note: ADC0CON 0xFFFF050C 0x0002 Read/Write The Current Channel ADC Control MMR is an 16-bit register that is used to configure the I-ADC. If the Current ADC is reconfigured via ADC0CON, the Voltage and Temperature ADCs are also reset.
Table 24 : ADC0CON MMR Bit Designations
Bit 15
Description Current Channel ADC Enable This bit is set to 1 by user code to enable the I-ADC Clearing this bit to 0, powers down the I-ADC and resets the respective ADC READY bit in the ADCSTA MMR to 0
14, 13
IIN Current Source Enable 0, 0 0, 1 1, 0 1, 1 Current Sources Off Enable 50uA current source on IIN+ Enable 50uA current source on IINEnable 50uA current source on both IIN- and IIN+
NOTE: These current sources have a tolerance of +-30%. A PGA gain equal to or greater than 2 ( ADC0CON [3-0 ] != 0000 ) must be used when current sources are enabled. 12- 10 9 Not Used These bits are reserved for future functionality and should be written as zero Current Channel ADC Output Coding This bit is set to 1 by user code to configure I-ADC output coding as unipolar This bit is cleared to 0 by user code to configure I-ADC output coding as 2's complement 8 7, 6 Not Used This bit is reserved for future functionality and should be written as zero Current Channel ADC Input Select 0, 0 0, 1 1, 0 IIN+, IINIIN-, IINDiagnostic, internal short configuration ADC Reference/136, 0V Diagnostic, test voltage for gain settings <= 128 ADC Reference/(1.0625XGain), 0V Diagnostic, test voltage for gain settings > 128 Note: If (REG_AVDD, AGND) divided by 2 Reference is selected, REG_AVDD is used for Vref in this mode. This will lead to ADC0DAT scaled by two Not Defined Internal, 1.2V precision reference selected. In ADC Low Power Mode, the Voltage Reference selection is controlled by ADCMDE[5] External reference inputs (VREF, GND_SW) selected External reference inputs divided by 2 (VREF, GND_SW)/2 selected, this allows an external reference up to REG_AVDD (REG_AVDD, AGND) divided by 2 selected
1, 1 5, 4 0, 0 0, 1 1, 0 1, 1
Current Channel ADC Reference Select
Rev. PrD | Page 52 of 128
Preliminary Technical Data
3-0 Current Channel ADC Gain Select (note, nominal I-ADC Full-scale Input Voltage = (Vref/GAIN) 0, 0, 0, 0 0, 0, 0, 1 0, 0, 1, 0 0, 0, 1, 1 0, 1, 0, 0 0, 1, 0, 1 0, 1, 1, 0 0, 1, 1, 1 1, 0, 0, 0 1, 0, 0, 1 1, x, x, x I-ADC Gain =1 I-ADC Gain =2 I-ADC Gain =4 I-ADC Gain =8 I-ADC Gain =16 I-ADC Gain =32 I-ADC Gain =64 I-ADC Gain =128 I-ADC Gain =256 I-ADC Gain =512 I-ADC Gain is undefined
ADUC7032
Voltage Channel ADC Control Register :
Name : Address : Default Value : Access : Function : Note: Bit 15 ADC1CON 0xFFFF0510 0x0000 Read/Write The Voltage Channel ADC Control MMR is an 16-bit register that is used to configure the V-ADC. When enabling/disabling the Voltage ADC, the Voltage Attenuator must also be enabled/disabled via HVCFG1[7].
Table 25 : ADC1CON MMR Bit Designations
Description Voltage Channel ADC Enable This bit is set to 1 by user code to enable the V-ADC. When enabling/disabling the Voltage ADC, the Voltage Attenuator must also be enabled/disabled via HVCFG1[7]. Clearing this bit to 0, powers down the V-ADC.
14- 10 9
Not Used These bits are reserved for future functionality and should not be modified by user code Voltage Channel ADC Output Coding This bit is set to 1 by user code to configure V-ADC output coding as unipolar This bit is cleared to 0 by user code to configure V-ADC output coding as 2's compliment
8 7, 6
Not Used This bit is reserved for future functionality and should be written as 0 by user code Voltage Channel ADC Input Select 0, 0 0, 1 1, 0 1, 1 VBAT/24, AGND Not Defined Not Defined Internal Short VBAT attenuator selected Shorted Input
5, 4
Voltage Channel ADC Reference Select 0, 0 0, 1 1, 0 1, 1 Internal, 1.2V precision reference selected. External reference inputs (VREF, GND_SW) selected. External reference inputs divided by 2 (VREF, GND_SW)/2 selected. This allows an external reference up to REG_AVDD (REG_AVDD, AGND) divided by 2 selected.
3-0
Not Used These bits are reserved for future functionality and should be written as 0 by user code
Rev. PrD | Page 53 of 128
Preliminary Technical Data
Temperature Channel ADC Control Register :
Name : Address : Default Value : Access : Function : Note: ADC2CON 0xFFFF0514 0x0000 Read/Write
ADUC7032
The Temperature Channel ADC Control MMR is an 16-bit register that is used to configure the T-ADC. The Temperature channel is calibrated to read 0x0000 at 0K. The temperature gradient is then 16 codes per degree Celsius
Table 26 : ADC2CON MMR Bit Designations
Bit 15
Description Temperature Channel ADC Enable This bit is set to 1 by user code to enable the T-ADC Clearing this bit to 0, powers down the T-ADC
14, 13
VTEMP Current Source Enable 0, 0 Current Sources Off 0, 1 Enable 50uA current source on VTEMP+ 1, 0 Enable 50uA current source on GND_SW 1, 1 Enable 50uA current source on both VTEMP+ and GND_SW NOTE: These current sources have a tolerance of +-30%.
12- 10 9
Not Used These bits are reserved for future functionality and should not be modified by user code Temperature Channel ADC Output Coding This bit is set to 1 by user code to configure T-ADC output coding as unipolar This bit is cleared to 0 by user code to configure T-ADC output coding as 2's compliment
8 7, 6
Not Used This bit is reserved for future functionality and should be written 0 by user code Temperature Channel ADC Input Select 0, 0 0, 1 1, 0 1, 1 Internal Temperature Sensor The Temperature gradient is 0.5mV/C. This is only applicable to the Internal Temperature Sensor External ( VTEMP, GND_SW) Shorted Input ( GND_SW, GND_SW) ADC Reference/136 Internal, 1.2V precision reference selected. External reference inputs (VREF, GND_SW) selected. External reference inputs divided by 2 (VREF, GND_SW)/2 selected. This allows an external reference up to REG_AVDD (REG_AVDD, GND_SW) divided by 2 selected. Used for external temperature sensor measurements.
5, 4
Temperature Channel ADC Reference Select 0, 0 0, 1 1, 0 1, 1
3-0
Not Used This bit is reserved for future functionality and should be written 0 by user code
Rev. PrD | Page 54 of 128
Preliminary Technical Data
ADC Filter Register :
Name : Address : Default Value : Access : Function : Note: ADCFLT 0xFFFF0518 0x0007 Read/Write
ADUC7032
The ADC Filter MMR is an 16-bit register that controls the speed and resolution of the on-chip ADCs. If ADCFLT is modified, the Current, Voltage and Temperature ADCs are reset. An additional time of 60us per enabled ADC is required before the first ADC result is available.
Table 27 : ADCFLT MMR Bit Designations
Bit 15
Description Chop enable Set by user to enable system chopping of all active ADCs. When this bit is set the ADC will have very low offset errors and drift but the ADC output rate will be reduced by a factor of 3 if AF=0 (see Sinc3 Decimation Factor bits below). If AF 0, then ADC output update rate will be the same with chop on or off. When chop is enabled, the settling time is 2 output periods. Note: Should only be used with SF > 1 Running Average Set by user to enable a running average by 2 function reducing ADC noise. This function is automatically enabled when chopping is active. It is an optional feature when chopping is inactive and if enabled (when chopping is inactive) does not reduce ADC output rate but will increase the settling time by 1 conversion period. Cleared by user to disable the running average function. Averaging Factor ( AF ) The value written to these bits is use to implement a programmable 1st order Sinc post filter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Sinc Decimation Factor bits below. Sinc3 Modify Set by user to modify the standard Sinc3 frequency response to increase the filter stopband rejection by 5dBs approx. This is achieved by inserting a second notch (NOTCH2) at FNOTCH2 = 1.333 * FNOTCH where FNOTCH is the location of the 1st notch in the response. Sinc3 Decimation Factor (SF) The value (SF) written in these bits controls the over sampling (decimation factor) of the Sinc3 filter. The output rate from the Sinc3 filter is given by FADC = ( 512,000 / ( [SF+1] X 64 )) Hz when the CHOP bit (bit#15 above) = 0 and AF=0 (note AF = Averaging Factor) Note : this is valid for all SF values <= 125 For SF= 126, FADC is forced to 60Hz For SF= 127, FADC is forced to 50Hz For information on calculating the FADC for SF ( other than 126 and 127 ) and AF values please refer to Table 28. Note: - Due to limitations on the digital filter internal data-path, there are some limitations on the combinations of SF(Sinc3 Decimation Factor) and AF(Averaging Factor) that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in Normal Power Mode to 4Hz or 1Hz in Low Power Mode. If all three ADCs are enabled, then the minimum value of SF written by user code must be 1 - In low power mode and low power-plus mode, the ADC is driven directly by the low power oscillator (131KHz) and not 512KHz. All FADC calculations should be divided by 4 (approx). - For optimal ADC performance, SF should be increased before AF is used.
14
13 - 8
7
6-0
Rev. PrD | Page 55 of 128
Preliminary Technical Data
Table 28 : ADC Conversion Rates and Settling Times
ADUC7032
Chop Enabled No
Running Average No
Averaging Factor No
FADC
*TSettling
512000 [ SF + 1] * 64
3
FADC
No
No
Yes
512000 [ SF + 1] * 64 *[3 + AF ]
512000 [ SF + 1] * 64 512000 [ SF + 1] * 64 * [3 + AF ]
512000 (SF+1) x 64 x (AF+3) + 3
1
FADC
No
Yes
No
4
FADC
No
Yes
Yes
2
FADC
Yes
N/A
N/A
2
FADC
*An additional time of 60us per enabled ADC is required before the first ADC result is available.
Table 29 : Allowable Combinations of SF and AF
AF Range SF 0-31 32-63 64-127 0 1 to 7 8 to63
Rev. PrD | Page 56 of 128
Preliminary Technical Data
ADC Configuration Register :
Name : Address : Default Value : Access : Function : Bit 7 ADCCFG 0xFFFF051C 0x00 Read/Write The 8-bit ADC Configuration MMR controls extended functionality related to the on-chip ADCs.
Table 30: ADCCFG MMR Bit Designations
ADUC7032
Description Analog Ground Switch Enable This bit is set to `1' by user software to connect the external `GND_SW' pin (pin#15) to an internal analog ground reference point. This bit can be used to connect and disconnect external circuits and components to ground under program control and thereby minimize dc current consumption when the external circuit or component is not being used. This bit is used in conjunction with ADCMDE[6] to select a 20K resistor to ground. Current Channel (32-bit) Accumulator Enable 0, 0 Accumulator Disabled and reset to 0 0, 1 Accumulator Active Positive current values are added to accumulator total, accumulator can overflow if allowed run for > 65535 conversions Negative current values are subtracted from accumulator total, accumulator is clamped to a minimum value of 0 1, 0 Accumulator Active Positive current values are added to accumulator total, accumulator can overflow if allowed run for > 65535 conversions The absolute values of Negative current are subtracted from accumulator total, accumulator in this mode will continue to accumulate negatively, below 0 1, 1 Accumulator and Accumulator Comparator Enabled This mode is the same as Mode |1,0|, but with the Accumulator Comparator enabled. Current Channel ADC Comparator Enable 0, 0 Comparator Disabled 0, 1 Comparator Active, Interrupt asserted if absolute value of I-ADC conversion result |I| >= ADC0TH 1, 0 Comparator-Count Mode Active, Interrupt asserted if absolute value of an I-ADC conversion result |I| >= ADC0TH for #ADC0TCL conversions. A conversion value |I| < ADC0TH will reset the threshold counter value (ADC0THV) to 0 1, 1 Comparator-Count Mode Active, Interrupt asserted if absolute value of an I-ADC conversion result |I| >= ADC0TH for #ADC0TCL conversions. A conversion value |I| < ADC0TH will decrement the threshold counter value (ADC0THV) towards 0. Current Channel ADC OverRange Enable Set by user to enable a `coarse' comparator on the Current Channel ADC. If the current reading is grossly (>30% approx.) over-ranged for the active gain setting, then the over range bit in the ADCSTA MMR is set. The current must be outside this range for greater than 125usecs for the flag to be set. This feature should not be used in ADC Low Power Mode ADC FIFO Enable This bit is set to 1 by user code to enable ADC FIFO on Current and Voltage ADC Channels. The FIFO function allows up to 32 current and voltage ADC results to be stored in an on-chip FIFO. The current status of the FIFO is reflected by 3 bits in the ADCSTA register. If more than 32 results are stored in the FIFO, the contents of the FIFO may be corrupted. Current Channel ADC, Result Counter Enable Set by user to enable the result count mode. In this mode an I-ADC interrupt will only be generated when ADC0RCV=ADC0RCL. This allows the I-ADC to continuously monitor current but only interrupt the MCU core after a defined number of conversions. It should be noted that unless the ADC FIFO is enabled (ADCCNG[1]=1), only the last conversion value will be available (intermediate I-ADC conversion results are not stored) when the ADC counter interrupt occurs. The Voltage and Temperature ADCs will also continue to convert if enabled but again only the last conversion result will be available (intermediate V/T-ADC conversion results are not stored) when the ADC counter interrupt occurs
6, 5
4, 3
2
1
0
Rev. PrD | Page 57 of 128
Preliminary Technical Data
Current Channel ADC Data Register :
Name : Address : Default Value : Access : ADC0DAT 0xFFFF0520 0x0000 Read Only Name : Address : Default Value : Access :
ADUC7032
Current Channel ADC Offset Calibration Register :
ADC0OF 0xFFFF0530 Part Specific, factory programmed Read/Write
Function : This ADC Data MMR holds the 16-bit conversion result from the I-ADC. The ADC will not update this MMR if the ADC0 Conversion Result READY bit (ADCSTA[0]) is set. A read of this MMR by the MCU clears all asserted READY flags (ADCSTA[2:0]).
Voltage Channel Data Register:
Name : Address : Default Value : Access : ADC1DAT 0xFFFF0524 0x0000 Read Only
Function : This ADC Offset MMR holds a 16-bit offset calibration coefficient for the I-ADC. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if an offset calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.
Voltage Channel Offset Calibration Register :
Name : Address : Default Value : Access : ADC1OF 0xFFFF0534 Part Specific, factory programmed Read/Write
Function : This ADC Data MMR holds the 16-bit conversion result from the V-ADC. The ADC will not update this MMR if the Voltage Conversion Result READY bit (ADCSTA[1]) is set. If I-ADC is not active, a read of this MMR by the MCU clears all asserted READY flags (ADCSTA[2:1]).
Temperature Channel ADC Data Register :
Name : Address : Default Value : Access : ADC2DAT 0xFFFF0528 0x0000 Read Only
Function : This Offset MMR holds a 16-bit offset calibration coefficient for the voltage channel. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if an offset calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.
Function : This ADC Data MMR holds the 16-bit conversion result from the T-ADC. The ADC will not update this MMR if the Temperature Conversion Result READY bit (ADCSTA[2]) is set.
Temperature Channel Offset Calibration Register:
Name : Address : Default Value : Access : ADC2OF 0xFFFF0538 Part Specific, factory programmed Read/Write
ADC FIFO Register :
Name : Address : Default Value : Access : ADCFIFO 0xFFFF052C 0x0000 Read Only
Function : This 32-bit, read-only register returns the value of I-ADC and V-ADC conversion result held in the FIFO location currently pointed to by the FIFO read pointer. The low 16 bits [15-0] of this 32-bit word are the I-ADC result and the high 16-bits [31-16] are the V-ADC result. The FIFO function is enabled via the ADCCFG[1] bit and 3 flags available in the ADCSTA register allow user code monitor and read the FIFO contents.
Function : This ADC Offset MMR holds a 16-bit offset calibration coefficient for the temperature channel. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if an offset calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.
Rev. PrD | Page 58 of 128
Preliminary Technical Data
Current Channel ADC Gain Calibration Register :
Name : Address : Default Value : Access : ADC0GN 0xFFFF053C Part Specific, factory programmed Read/Write
ADUC7032
Current Channel ADC Result Counter Limit Register:
Name : Address : Default Value : Access : ADC0RCL 0xFFFF0548 0x0001 Read/Write
Function : This Gain MMR holds a 16-bit gain calibration coefficient for scaling the I-ADC conversion result. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if aa gain calibration of the I-ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.
Function : This 16-bit MMR sets the number of conversions required before an ADC interrupt is generated. By default this register is set to 0x01. The ADC counter function must be enabled via the ADC Result Counter Enable bit in the ADCCFG MMR.
Current Channel ADC Result Count Register:
Name : Address : Default Value : Access : ADC0RCV 0xFFFF054C 0x0000 Read Only
Voltage Channel Gain Calibration Register :
Name : Address : Default Value : Access : ADC1GN 0xFFFF0540 Part Specific, factory programmed Read/Write
Function : This Gain MMR holds a 16-bit gain calibration coefficient for scaling a voltage channel conversion result. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if a gain calibration of the voltage channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.
Function : This 16-bit, Read Only MMR holds the current number of I-ADC conversion results. It is used in conjunction with ADC0RCL to mask I-ADC interrupts, generating a lower interrupt rate. Once ADC0RCV=ADC0RCL, the value is ADC0RCV resets to 0 and recommences counting. It can also be used in conjunction with the Accumulator (ADC0ACC) to allow an average current calculation to be undertaken. The result counter is enabled via ADCCFG[0]. This MMR is also reset to 0 when the I-ADC is reconfigured i.e. when the ADC0CON or ADCMDE are written.
Current Channel ADC Threshold Register:
Name : Address : Default Value : Access : ADC0TH 0xFFFF0550 0x0000 Read/Write
Temperature Channel Gain Calibration Register :
Name : Address : Default Value : Access : ADC2GN 0xFFFF0544 Part Specific, factory programmed Read/Write
Function : This Gain MMR holds a 16-bit gain calibration coefficient for scaling a temperature channel conversion result. The register is configured at power-on with a factory default value. However, this register will be automatically overwritten if a gain calibration of the temperature channel is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. A delay of 23us should be included before ADCMDE is modified.
Function : This 16-bit MMR sets the threshold against which the absolute value of the I-ADC conversion result is compared. In Unipolar mode ADC0TH [15:0] are compared and in 2's compliment mode ADC0TH[14:0] are compared.
Current Channel ADC Threshold Count Limit Register:
Name : Address : Default Value : Access : ADC0TCL 0xFFFF0554 0x01 Read/Write
Function : This 8-bit MMR determines how many cumulative(given values below the threshold will decrement or reset the count to 0) I-ADC conversion result readings above ADC0TH must occur before the I-ADC Comparator Threshold
Rev. PrD | Page 59 of 128
Preliminary Technical Data
bit is set in the ADCSTA MMR generating an ADC interrupt. The I-ADC Comparator Threshold bit is asserted as soon as the ADC0THV=ADC0TCL.
ADUC7032
If the LPM Voltage Reference is 1% below1.200V,then the value of ADCREF will be approximately 0x7EB9 If the LPM Voltage Reference is 1% above1.200V,then the value of ADCREF will be approximately 0x8147
Current Channel ADC Threshold Count Register:
Name : Address : Default Value : Access : ADC0THV 0xFFFF0558 0x00 Read Only
ADC POWER MODES OF OPERATION
The ADCs can be configured into various reduced or full `power' modes of operation by configuring ADCMDE[4:3] as appropriate. The ARM7 MCU can itself also be configured in Low Power modes of operation (POWCON[5:3]). The core power modes are independently controlled and are not related to the ADC power modes described here. The ADC power modes of operation are described in more detail below. Every I-ADC result can also compared to a pre-set threshold level (ADC0TH) as configured via ADCCFG[4:3]. An MCU interrupt is generated if the absolute (sign-independent) value of the ADC result is greater than the pre-programmed comparator threshold level. An extended function of this comparator function allows user code to configure a threshold counter (ADC0THV) which monitors the number of I-ADC results that have occurred above or below the pre-set threshold level. Again an ADC interrupt is generated once the threshold counter reaches a pre-set value (ADC0TCL). Finally, a 32-bit accumulator(ADC0ACC) function can be configured(ADCCFG[6:5]) allowing the I-ADC to add(or subtract) multiple I-ADC sample results. User code can read the accumulated value directly( via ADC0ACC) without any further software processing.
Function : This 8-bit MMR is incremented every time the absolute value of an I-ADC conversion result |I| >= ADC0TH. This register is decremented or reset to 0 every time the absolute value of an I-ADC conversion result |I| < ADC0TH. The configuration of this function is enabled via the Current Channel ADC Comparator bits in the ADCCFG MMR
Current Channel ADC Accumulator Register:
Name : Address : Default Value : Access : ADC0ACC 0xFFFF055C 0x00000000 Read Only
Function : This 32-bit MMR holds the current accumulator value. The I-ADC READY bit in the ADCSTA MMR should be used to determine when it is safe to read this MMR. The MMR value is reset to 0 by disabling the accumulator in the ADCCFG MMR or reconfiguring the Current Channel ADC.
Current Channel ADC Accumulator Threshold Register:
Name : Address : Default Value : Access : ADC0ATH 0xFFFF0560 0x00000000 Read/Write
ADC Startup Procedure
Prior to beginning converting, the following procedure should be followed. 1. Configure the Current ADC, ADC0, into Low-PowerMode (ADC0CON = 0x8007; ADCMDE = 0x09) Delay for 200us. Switch the Current ADC, ADC0, into Idle-Mode (ADCMDE = 0x03), keeping ADC0CON unchanged. If the Voltage or Temperature channels are to be used, they should be enabled here. Delay for 1ms Switch ADCMDE to desired mode, e.g. ADC0CON = 0x1.
Function : This 32-bit MMR sets the threshold against which the accumulated value of the I-ADC results is compared. In Unipolar mode ADC0TH [15:0] are compared and in 2's compliment mode ADC0TH[14:0] are compared.
2. 3.
Low Power Voltage Reference Scaling Factor
Name : Address : Default Value : Access : ADCREF 0xFFFF057C Part Specific, factory programmed Read 4. 5.
Function : This allows user code to correct for the initial error of the LPM reference. The default value of 0x8000 corresponds to no error when compared to the Normal Mode Reference.
Rev. PrD | Page 60 of 128
Preliminary Technical Data
ADC Normal Power Mode
In Normal Mode, the Current and Voltage/Temperature channels are fully enabled. The ADC modulator clock is 512KHz and enables the ADCs to provide regular conversion results at a rate of between 4Hz and 8KHz (see ADCFLT). Both channels are under full control of the MCU and can be reconfigured at any time. The default ADC update rate for all channels in this mode is 1.0kHz It is worth emphasizing that I-ADC and V/T-ADC channels can be configured to initiate periodic, normal power mode, high accuracy, single conversion cycles before returning to ADC full power-down mode. This flexibility is facilitated under full MCU control via the ADCMDE MMR and ensures that continuous periodic monitoring of battery current, voltage and temperature settings is feasible while ensuring the average dc current consumption is minimized. In ADC Normal Mode, the PLL must not be powered down.
ADUC7032
digital comparator and accumulator) described earlier in normal power mode can still be enabled in Low Power-Plus mode. As in Low Power Mode, the I-ADC only, is configured to run at a low update rate, continuously monitoring battery current. The MCU will be in power-down mode and will only be woken up when the I-ADC interrupts the MCU. This would happen after the I-ADC detects a current conversion result or an accumulated current value has risen beyond a pre-programmed threshold or set-point. It is also possible to select either the ADC Normal Mode Voltage Reference of the ADC Low Power Mode Voltage Reference via ADCMDE[5].
ADC Sinc3 Digital Filter Response
The overall frequency response on all ADUC7032s ADCs is dominated by the low pass filter response of the on-chip Sinc3 digital filters. The Sinc3 filters are used to decimate the ADC sigma-delta modulator output data bit-stream to generate a valid 16-bit data result. The digital filter response is identical for all ADCs and is configured via the 16-bit ADC Filter (ADCFLT) register which determines the overall throughput rate of the ADCs. The noise resolution of the ADCs is determined by the programmed ADC throughput rate. In the case of the Current Channel ADC, the noise resolution will be determined by throughput rate and selected gain. The overall frequency response and the ADC through-put is dominated by the configuration of the Sinc3 Filter Decimation Factor (SF) bits (ADCFLT[6:0]) and the Averaging Factor (AF) bits(ADCFLT[13:8]). Due to limitations on the digital filter internal data-path, there are some limitations on the allowable combinations of SF(Sinc3 Decimation Factor) and AF(Averaging Factor) that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in Normal Power Mode to 4Hz or 1Hz in Low Power Mode. The calculation of the ADC through-put rate is detailed in the ADCFLT bit designations table and the restrictions on allowable combinations of AF and SF values are outlined again in Table 31
Table 31 : Allowable Combinations of SF and AF
ADC Low Power Mode
In ADC Low Power mode, the I-ADC is enabled in a reduced power and reduced accuracy configuration. The ADC modulator clock is now driven directly from the on-chip 131KHz low power oscillator, which allows the ADC to be configured at update rates as low as 1Hz(ADCFLT). The gain of the ADC in this mode is fixed at 128. All of the ADC peripheral functions (result counter, digital comparator and accumulator) described earlier in normal power mode can still be enabled in low power mode. Typically, in Low Power Mode, the I-ADC only, is configured to run at a low update rate, continuously monitoring battery current. The MCU will be in power-down mode and will only be woken up when the I-ADC interrupts the MCU. This would happen after the I-ADC detects a current conversion or an accumulated current value has risen beyond a pre-programmed threshold, set-point or a set number of conversions. It is also possible to select either the ADC Normal Mode Voltage Reference of the ADC Low Power Mode Voltage Reference via ADCMDE[5].
AF Range
ADC Low Power-Plus Mode
In Low Power-Plus mode, the I-ADC channel is enabled in a mode almost identical to low-power mode(ADCMDE[4:3]). However, in this mode, the I-ADC gain is fixed at 512 and the ADC consumes an additional 200uA (approx.) to yield improved noise performance relative to the low-power mode setting. Again, all of the ADC peripheral functions (result counter,
SF <= 31 63 127
0
1 to 7
8-63
Rev. PrD | Page 61 of 128
Preliminary Technical Data
By default the ADCFLT = 0x07 which configures the ADCs for a through-put of 1.0KHz with all other filtering options (Chop, Running Average, Averaging Factor and Sinc3 Modify) being disabled. A typical filter response based on this default configuration is shown in Figure 19 below.
H(f) [dB] 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 500 1000 1500 2000 2500 3000 3500 4000 4500 f 5000 H(f) [dB] 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 2000 4000 6000 8000 10000 12000 14000 16000
ADUC7032
f [Hz] 18000 20000 22000 24000
Figure 21 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x0000)
Figure 19 : Typical Digital Filter Response at FADC=1.0kHz (ADCFLT = 0x0007)
An additional `Sinc3 Modify' bit (ADCFLT[7]) is also available in the ADCFLT register. This bit is set by user code to modify the standard Sinc3 frequency response increasing the filter stopband rejection by 5dBs approx. This is achieved by inserting a second notch (NOTCH2) at FNOTCH2 = 1.333 X FNOTCH where FNOTCH is the location of the 1st notch in the response. There is a slight increase in ADC noise if this bit is active. Figure 20 shows the modified 1KHz filter response when the Sinc3 modify bit is active. The `new' notch is clearly visible at 1.33KHz as is the improvement in stop-band rejection when compared to the standard 1KHz response above.
A modified version of the 8KHz filter response can be configured by setting the `Running Average' bit (ADCFLT[14]). This has the effect of introducing an additional running average by 2 filter on all ADC output samples. This further reduces the ADC output noise and while maintaining an 8KHz ADC through-put rate the ADC settling time is increased by 1 full conversion period. The modified frequency response for this configuration is shown below in Figure 22.
H(f) [dB]
0 -10 -20 -30 -40 -50 -60
H(f) [dB]
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
-70 -80 -90 -100 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 22000 f [Hz] 24000
Figure 22 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x4000)
-100 0 500 1000 1500 2000 2500 3000 3500 4000 4500
f 5000
Figure 20 : ModifiedSinc3 Digital Filter Response at FADC=1.0kHz (ADCFLT = 0x0087)
At very low throughput rates, the chop bit in the ADCFLT register can be enabled to minimize offset errors and more importantly and temperature drift in the ADC DC errors. With Chop enabled, there are again 2 primary variables (Sinc3 decimation factor and averaging factor) available to allow the user select an optimum filter response trading off filter bandwidth against ADC noise. For example, with the CHOP bit ADCFLT[15] set to 1, increasing the SF value (ADCFLT[6:0]) to 0x1F (31dec) and selecting an AF value (ADCFLT[13:8]) of 0x16 (22dec) results in an ADC through-put of 10Hz. The frequency response in this case is shown in Figure 23.
In ADC Normal Power Mode, the maximum ADC through-put rate is 8KHz which is configured by setting the SF and AF bits in the ADCFLT MMR to 0, with all other filtering options disabled. This results in 0x0000 written to ADCFLT and a typical 8KHz filter response based on these settings is shown below in Figure 21.
Rev. PrD | Page 62 of 128
Preliminary Technical Data
H(f) [dB] 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 20 40 60 80 100 120 140 160 180 f 200 H(f) [dB] 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 2 4 6 8 10 12 14
ADUC7032
f 16 18 20
Figure 23 Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x961F)
Figure 25 : Typical Digital Filter Response at FADC=1Hz, (ADCFLT = 0xBD1F
Changing SF to 0x1D and setting AF to 0x3F, again with the Chop bit enabled, configures the ADC into its minimum through-put rate in Normal Mode of 4Hz. The digital filter frequency response with this configuration is shown below in Figure 24.
H(f) [dB] 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 20 40 f 60
In general, it should be noted that it is possible to program different values of SF and AF in the ADCFLT register and achieve the same ADC update rate. In practical terms the tradeoff with any value of ADCFLT will be frequency response versus ADC noise. For optimum filter response and ADC noise when using combinations of SF and AF, a good rule of thumb to use would be to first choose an SF in the range of 16 - 40 (dec) or 0x10 to 0x28 and then increase the AF value to achieve the required ADC through-put. Table 32 shows some common ADCFLT configurations.
Table 32 : Common ADCFLT Configurations
ADC Mode
Normal
SF
0x1D
AF
0x3F
Other Config
Chop On
ADCFLT
0xBF1D
FADC
4Hz
TSETTLE
0.5secs
Normal
0x1F
0x16
Chop On
0x961F
10Hz
0.2secs
Figure 24 : Typical Digital Filter Response at FADC=4Hz, (ADCFLT = 0xBF1D) Normal 0x07 0x00 None Sinc 3 Modifiy Running Average Running Average Chop On 0x0007 1KHz 3msecs
In ADC Low Power Mode, the ADC, Sigma-Delta modulator clock no longer driven at 512KHz but is driven directly from the on-chip low power (131KHz) oscillator. Subsequently, for the same ADCFLT configurations in Normal Mode, all filter values should be scaled by a factor of approximately 4. This means that is possible to configure the ADC for 1Hz throughput is Low Power Mode. The filter frequency response for this configuration is shown below in Figure 25.
Normal
0x07
0x00
0x0087
1KHz
3msec
Normal
0x03
0x00
0x4003
2KHz
2msec
Normal Low Power Low Power Low Power
0x00
0x01
0x4000
8KHz
0.5ms
0x10
0x03
0x8310
20Hz
100ms
0x10
0x09
Chop On
0x8910
10Hz
200ms
0x1F
0x3D
Chop On
0xBD1F
1Hz
2sec
Rev. PrD | Page 63 of 128
Preliminary Technical Data
ADC Calibration
As described in detail in the top level diagrams at the start of this section, the signal flow through all ADC Channels can be described in simple terms as: An Input-voltage is applied through an input buffer (and PGA in the case of the I-ADC) to the SigmaDelta Modulator. The Modulator-output is applied to a programmable Digital Decimation Filter The filter output result is then averaged if chopping is used. An Offset value (ADCxOF) is subtracted from the result. This result is scaled by a Gain value (ADCxGN). Finally, the result is formatted as - 2's Complement. / Offset-Binary, - Rounded to 16-Bit - Clamped to +/-Full-Scale Each ADC has a specific Offset and Gain correction or Calibration coefficient associated with it that are stored in MMR based Offset and Gain registers(ADCxOF and ADCxGN). The offset and gain registers can be used to remove offsets and gain errors arising within the part as well as Systemlevel offset and gain errors external to the part. These registers are configured at power-on with a factory programmed calibration value. These factory calibration values will vary from part to part reflecting the manufacturing variability of internal ADC circuits . However, these registers can also be overwritten by user code (only if the ADC is in idle mode) and will be automatically overwritten if an offset or gain calibration cycle is initiated by user via the mode bits in the ADCMDE[2:0] MMR. 2 types of automatic calibration are available to the user, namely : - Self (Offset or Gain) Calibration, where the ADC generates its calibration coefficient based on an internally generated 0V in the case of Self-Offset calibration and full-scale voltage in the case of Self-Gain calibration. It should be emphasized that ADC SelfCalibrations correct for offset and gain errors within the ADC. Self calibrations cannot compensate for other external errors in the system, e.g. Shunt-Resistor tolerance/drift, external offset voltages etc. - System (Offset or Gain) Calibration, where the ADC generates its calibration coefficient based on an externally generated zero-scale voltage in the case of System-Offset calibration and Full-scale voltage in the case of System-Gain calibration which are applied to the external ADC input for the duration of the calibration cycle.
Rev. PrD | Page 64 of 128
ADUC7032
The duration of an Offset calibration is 1 single conversion cycle (3/FADC Chop off, 2/FADC Chop on) before returning the ADC to idle mode. A Gain calibration is a 2 stage process and subsequently takes twice as long as an offset calibration cycle. Once a calibration cycle is initiated, any ongoing ADC conversion is immediately halted, the calibration is carried out automatically at an ADC update rate programmed into ADCFLT and the ADC is always returned to idle after any calibration cycle. It is strongly recommended that ADC calibration is initiated at as low an ADC update rate as possible (high SF value in ADCFLT) in order to minimize the impact of ADC noise during calibration. NOTE: ADC0OF and ADC0GN must first contain the values for PGA = 1 before a calibration scheme is started
Using the Offset and Gain Calibration Registers
If the Chop bit (ADCFLT[15]) is enabled, then internal ADC offset errors will be minimized and an Offset calibration may not be required. If chopping is disabled however, an initial Offset calibration will be required and may need to be repeated. A Gain calibration, particularly in the context of the I-ADC (with internal PGA) may need to be carried out at all relevant system gain ranges depending on system accuracy requirements. If it is not possible to apply an external full-scale current on all gain ranges then it is possible to apply a lower current, and scale the result produced by the calibration. e.g Apply a 50% current and then divide the ADC0GN value produced by 2 and write this value back into ADC0GN. It should be noted that there is a lower limit to the input signal that can be applied for a System-Calibration because the ADC0GN register is only 16-Bit. The input span (difference between the System Zero-Scale value and System Full-Scale value) should be greater than 40% of the nominal Full-ScaleInput range, ie > 40% of Vref/Gain. The on-chip Flash/EE memory can be used to store multiple calibration coefficients which can be copied by user code directly into the relevant calibration registers as appropriate based on system configuration. In general, the simplest way to use the calibration registers is to let the ADC calculate the values required as part of the ADC automatic calibration modes.
Preliminary Technical Data
A factory or end-of-line calibration for the I-ADC would be a 2-step procedure: 1. Apply 0A current. Configure the ADC in the required PGA setting etc. and write to ADCMDE[2:0] to perform a System Zero-Scale Calibration. This writes a new offset calibration value into ADC0OF. 2. Apply a Full-Scale current for the selected PGA setting. Write to ADCMDE to perform a System Full-Scale Calibration. This writes a new gain calibration value into ADC0GN.
ADUC7032
gain error if this value is used at different PGA settings. User code can over-write the calibration coefficients or run ADC calibrations to correct the gain error at the current PGA setting. In Summary, the simplified ADC transfer function can be described as :
ADCGN VIN ADCOUT = - ADCOF * VREF ADCGNNOM
This equation is valid for Voltage/Temperature channel ADC. For the Current Channel ADC,
Understanding the Offset and Gain Calibration Registers
The output of the average block in the ADC signal flow described earlier after the digital filter and before the Offset and Gain scaling can be considered to be a fractional number with a span, for a +/- Full-Scale input, of approx +/-0.75. The span is less than +/-1.0 because there is attenuation in the modulator to accommodate some over-range capacity on the input signal. The exact value of the attenuation will vary slightly from partto-part, because of manufacturing tolerances. The Offset Coefficient is read from the ADC0OF calibration register. This value is a 16-Bit 2's complement number. The range of this number, in terms of the signal chain, is effectively +/-1.0. 1 LSB of the ADC0OF register is therefore not the same as 1LSB of ADC0DAT. A positive value of ADC0OF indicates that offset is subtracted from the output of the filter, a negative value is added. The nominal value of this register is 0x0000, indicating zero offset is to be removed. The actual offset of the ADC may vary slightly from part-to-part and at different PGA gains. The offset within the ADC is minimized if the Chopping mode is active (ADCFLT[15]=1). The Gain Coefficient is a unitless scaling factor. The 16-Bit value in this register is divided by 16384, and then multiplied by the offset-corrected value. The nominal value of this register equals 0x5555, which corresponds to a multiplication factor of 1.3333. This scales the nominal +/-0.75 signal to produce a fullscale output signal of +/-1.0 which is checked for Overflow/ Underflow and converted to Two's Complement or Unipolar mode as appropriate, before being output to the Data register. The actual gain, and the required scaling coefficient for zero gain error, varies slightly from part to part, and at different PGA settings and in Normal / Low-Power-Mode. The value downloaded into ADC0GN at power-on/reset represents the scaling factor for a PGA Gain=1. There will be some level of
ADCGN VIN ADCOUT = - K * ADCOF * VREF ADCGNNOM
where K is dependent on PGA gain setting and ADC mode. Normal Mode: For PGA gains of 1,4,8,16,32 and 64 the K factor is 1. For PGA gains of 2 and 128 the K factor is 2. For PGA gain of 256 the K Factor is 4. For PGA gain of 512, the K factor is 8. Low Power Mode: The PGA gain is set to 128 and the K factor is 32. Low Power Plus Mode: The K factor is 8. In Low-Power and Low-Power-Plus Mode, the K factor doubles if (AVDD_Reg)/2 is used as the reference.
ADC DIAGNOSTICS
The ADUC7032 features diagnostic capability on all three ADCs.
Current ADC Diagnostics
The ADUC7032 features the capability to detect Open Circuit conditions on the application board. This is accomplished using the two current sources on IIN+ and IIN-, which is controlled via ADC0CON[14,13]. The use of both the IIN+ and IIN- current sources is shown in Table 33. To verify the current ADC is converting correctly, it is possible to select an internal test voltage via ADC0CON[7,6]. Selecting mode 10 results in the current ADC converting the Voltage Reference, e.g. The Precision 1.2V Reference, divided by 136 for PGA settings less than or equal to 128 and divided by (1.0625*Gain) for PGA settings greater than 128.
Rev. PrD | Page 65 of 128
Preliminary Technical Data
Temperature ADC Diagnostics
The ADUC7032 features the capability to detect Open Circuit conditions on the Temperature Channel inputs. This is accomplished using the two current sources on VTEMP+ and GND_SW, which is controlled via ADC2CON[14,13]. The use of both the VTEMP+ and GND_SW current sources is shown in Table 34.
Table 33: Current ADC Diagnostics
ADUC7032
To verify the Temperature ADC is converting correctly, it is possible to select an internal test voltage via ADC2CON[7,6]. Selecting mode 10 results in the current ADC converting the Voltage Reference, e.g. The Precision 1.2V Reference, divided by 136.
Fault Condition
Short between IIN+ and IINat pins of device Short Between IIN+ and GND
Current Source Enabled
ADC0DAT Result
No difference between ADC0DAT result prior to and after IIN+ (or IIN-) current source is enabled No difference between ADC0DAT result prior to and after IIN+ current source is enabled No difference between ADC0DAT result prior to and after IINcurrent source is enabled
IIN+ or IIN-
IIN+
Short Between IIN- and GND
IIN-
IIN+ Open Circuit
IIN+
Positive Full Scale ( 0x7FFF in Bi Polar Mode )
IIN- Open Circuit
IIN-
Negative Full Scale ( 0x8000 in Bi Polar Mode )
Table 34: Temperature ADC Diagnostics
Fault Condition
Short between VTEMP+ and GND_SW at pins of device Short Between VTEMP+ and GND Short Between GND_SW and GND VTEMP+ Open Circuit
Current Source Enabled
ADC0DAT Result
No difference between reading prior to and after VTEMP+ or GND_SW current source is enabled No difference between reading prior to and after VTEMP+ current source is enabled No difference between reading prior to and after GND_SW current source is enabled
VTEMP+ or GND_SW
VTEMP+
GND_SW
VTEMP+
Positive Full Scale ( 0x7FFF in Bi Polar Mode )
GND_SW Open Circuit
GND_SW
Negative Full Scale ( 0x8000 in Bi Polar Mode )
Rev. PrD | Page 66 of 128
Preliminary Technical Data
POWER SUPPLY SUPPORT CIRCUITS
The ADUC7032 incorporates an on-chip Low Drop-Out(LDO) regulator which is driven directly from the battery voltage to generate a 2.6V internal supply. This 2.6V supply is then used as the supply voltage for the ARM7 MCU and peripherals including the precision analog circuits on-chip. Power on Reset(POR), Power Supply Monitor(PSM) and Low Voltage Flag (LVF) functions are also integrated to ensure safe operation of the MCU as well as continuously monitoring the battery power supply. The POR circuit is designed to handle all battery ramp rates and guarantee full functional operation of the Flash/EE memory based MCU during power-on and power-down cycles. As shown in Figure 26, once the supply voltage, VDD, reaches a minimum operating voltage of 3V, a POR signal keeps the ARM core in reset for 20ms. This ensures that the regulated power supply voltage. REG_DVDD, supplied to the ARM core and associated peripherals is above the minimum operational
12V PSM TRIP 6.0V TYP VDD 3V TYP POR TRIP 3.0V TYP LVF TRIP 2.1V TYP 2.6V REG_DV DD
ADUC7032
voltage to guarantee full functionality. A POR flag is set in the RSTSTA MMR to indicate a POR reset event has occurred The ADUC7032also features a PSM, or Power Supply Monitor function. Once enabled via HVCFG0[3], the PSM continuously monitors the voltage at the VDD pin. If this voltage drops below 6.0VTYP, the PSM flag is automatically asserted and can, if the high voltage IRQ is enabled via IRQ/FIQEN[16], generate a system interrupt. An example of this operation is shown in Figure 26. At voltages below the POR level, an additional Low Voltage Flag can be enabled (HVCFG0[2]). It may be used to indicate that the contents of the SRAM are still valid after a reset event. The operation of the low voltage flag is shown in Figure 26. Once enabled, the status of this bit may be monitored via HVSTA[6]. If this bit is set, then the SRAM contents are valid. If this bit is cleared, then the SRAM contents may have been corrupted.
20ms TYP
POR_TRIP
RESET_CORE (INTERNAL SIGNAL)
ENABLE_PSM
ENABLE_LVF
Figure 26: Typical Power-On Cycle
Rev. PrD | Page 67 of 128
05994-026
Preliminary Technical Data
ADUC7032 SYSTEM CLOCKS
The ADUC7032 integrates a highly flexible clocking system, which may be clocked from one of three sources: 1. 2. 3. An integrated on-chip precision oscillator An integrated on-chip low power oscillator. An external watch crystal
ADUC7032
generates a 20.48MHz clock source. The ARM7TDMI Core, is driven by a CD divided clock derived from the output of the PLL. By default, the CD divider is configured to divide the PLL output by 2, which generates a core clock of 10.24MHz. The divide factor may be modified to generate a binary weighted divider factor from 1 to 128, which may be altered dynamically by user code. The ADC is driven by the output of the PLL, divided to give an ADC clock source of 512kHz. In low-power mode the ADC clock source is switched from the standard 512kHz to the Low Power 131kHz oscillator. It should also be noted that the low power oscillator drives both the watchdog and core wake-up timers through a divide by 4 circuit. A detailed block diagram of the ADUC7032 clocking system is shown in Figure 27.
These three options are shown in Figure 27. Each of the internal oscillators are divided by 4 to generate a clock frequency of 32.768kHz. The PLL locks onto a multiple (625) of 32.768kHz, supplied by either of the internal oscillators or the external crystal, to provide a stable 20.48MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, which allows power saving if peak performance is not required. By default, the PLL is driven by the Low Power oscillator which
EXTERNAL CRYSTAL (OPTIONAL)
PRECISION 131kHz EXTERNAL 32.768kHz
HIGH ACCURCY CALIBRATION COUNTER
PRECISION 131kHz
CRYSTAL CIRCUITRY
LOW POWER 131kHz
LOW POWER OSCILLATOR EXTERNAL 32.768kHz PRECISION 32.768kHz LOW POWER 32.768kHz CORE CLOCK GPIO_5
LOW POWER CALIBRATION COUNTER
EXTERNAL 32.768kHz PRECISION OSCILLATOR PRECISION 32.768kHz DIV 4
LOW POWER OSCILLATOR LOW POWER 32.768kHz DIV 4 PLLCON
TIMER 0 LIFE TIME
PLL
ECLK 2.5MHz
GPIO_8 TIMER 1 CORE CLOCK LOW POWER 32.768kHz
1 8
PLL OUTPUT 20.48MHz
CLOCK DIVIDER
CORE CLOCK EXTERNAL 32.768kHz
PLL LOCK FLASH CONTROLLER 1 2CD CORE CLOCK MCU ADC CLOCK
ADCMDE
PRECISION 32.768kHz LOW POWER 32.768kHz LOW POWER 32.768kHz LOW POWER 32.768kHz
TIMER 2 WAKE-UP
WATCHDOG TIMER 3
ADC
TIMER 4 STI
CORE CLOCK LOW POWER 32.768kHz
CORE CLOCK PLL OUTPUT (20.48MHz) SPI CORE CLOCK UART
PLL OUTPUT (5MHz)
Figure 27: ADUC7032 System Clock Generation
Rev. PrD | Page 68 of 128
05994-027
LIN H/W SYNCHRONIZATION
Preliminary Technical Data
The operating mode, clocking mode and programmable clock divider are controlled via two MMRs, PLLCON and POWCON, and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clock system while POWCON controls the core clock frequency and the powerdown mode. PLLSTA indicates the presence of an oscillator on the XTAL1 pin, the PLL Lock status, and the PLL Interrupt. It is recommended that before the ADUC7032 is powered down, that the clock source for the PLL is switched to the Low Power 131kHz oscillator to reduce wake up time. The Low Power, Oscillator is always active. When the ADUC7032 wakes up from power down, the MCU core will begin executing code once the PLL begins oscillating. This occurs before the PLL has locked to a frequency of 20.48MHz. To ensure the Flash memory controller is executing with a valid clock, the controller is driven with a PLL-Output/8 clock source while the PLL is locking. Once the PLL locks, the PLL's output is switched from the PLL-Output/8 to the locked PLL-Output. If user code requires an accurate PLL output, user code must poll the Lock bit (PLLSTA[1]) after wake-up before resuming normal code execution.
ADUC7032
The PLL will be locked and executing user code within 2ms, if the PLL is clocked from an active clock source, e.g. Low Power 131kHz oscillator after waking up. PLLCON is a protected MMR with two 32 bit keys PLLKEY0, a pre write key, and PLLKEY1, a post write key. PLLKEY0 = 0x000000AA PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32 bit keys POWKEY0, a pre write key, and POWKEY1, a post write key. POWKEY0 = 0x00000001 POWKEY1 = 0x000000F4
An example of writing to both MMRs is shown below: POWKEY0 = 0x01 POWCON = 0x00 POWKEY1 = 0xF4 iA1*iA2 PLLKEY0 = PLLCON = 0xAA 0x0 //POWCON KEY //Full Power-down //POWCON KEY //dummy cycle //PLLCON KEY //Switch to Low //Power Osc. //PLLCON KEY //dummy cycle
PLLKEY1 = 0x55 iA1*iA2
PLLSTA Register :
Name : Address : Default Value : Access : Function : PLLSTA 0xFFFF0400 0x02 Read/Write This 8-bit register allows user code to monitor the lock state of the PLL and the status of the external crystal.
Table 35 : PLLSTA MMR Bit Description
Bit 31-3 2
Description Reserved and should be written as zeros XTAL Clock, Read Only This is a live representation of the current logic level on XTAL1. This allows the user to check to see if an external clock source is present. If present this bit will alternate high and low at a frequency of 32.768kHz. PLL Lock Status Bit, Read Only Set when the PLL is locked and outputting 20.48MHz. Clear when the PLL is not locked and outputting a Fcore/8 clock source PLL Interrupt: Set if the PLL Lock status bit signal goes low. Cleared by writing 1 to this bit
1
0
Rev. PrD | Page 69 of 128
Preliminary Technical Data
PLLCON Pre-write Key PLLKEY0:
Name : Address : Default Value : Access : Key: Function : PLLKEY0 0xFFFF0410 0x00000000 Write Only 0x000000AA PLLCON is a keyed register that requires a 32 Bit key value to be written before and after PLLCON. PLLKEY0 is the Pre-Write Key
ADUC7032
PLLCON Pre-write Key PLLKEY1:
Name : Address : Default Value : Access : Key: Function : PLLKEY1 0xFFFF0418 0x00000000 Write Only 0x00000055 PLLCON is a keyed register that requires a 32 Bit key value to be written before and after PLLCON. PLLKEY1 is the Post-Write Key
PLLCON Register :
Name : Address : Default Value : Access : Function : Bit 31-3 2 1-0 PLLCON 0xFFFF0414 0x00 Read/Write This 8-bit register allows user code dynamically select the PLL source clock from three different oscillator sources.
Table 36: PLLCON MMR Bit description
Description Reserved, these bits should be written as 0 by user code Not Used, must be written 0 by user software. PLL Clock Source1 00 Low Power 131kHz oscillator 01 10 11 Precision 131kHz oscillator External 32.768kHz Crystal Reserved
1
If user code switches MCU clock sources, a dummy MCU cycle should be included after the clock switch is written to PLLCON.
POWCON Pre-write Key POWKEY0:
Name : Address : Default Value : Access : Key: Function : POWKEY0 0xFFFF0404 0x00000000 Write Only 0x00000001 POWCON is a keyed register that requires a 32 Bit key value to be written before and after POWCON. POWKEY0 is the PreWrite Key
POWCON Pre-write Key POWKEY1:
Name : Address : Default Value : Access : Key: Function : POWKEY1 0xFFFF040C 0x00000000 Write Only 0x000000F4 POWCON is a keyed register that requires a 32 Bit key value to be written before and after POWCON. POWKEY1 is the PostWrite Key
Rev. PrD | Page 70 of 128
Preliminary Technical Data
POWCON Register :
Name : Address : Default Value : Access : Function :
ADUC7032
POWCON 0xFFFF0408 0x079 Read/Write This 8-bit register allows user code dynamically enter various Low Power modes and modify the CD divider which controls the speed of the ARM7TDMI Core.
Table 37 : POWCON MMR bit designations
Bit 31-8 7
6
5
4
3
2-0
Description Reserved Precision 131kHz Input Enable: Cleared by the user to Power down the Precision 131kHz Input Enable. Set by the user to enable the Precision 131kHz Input Enable. The Precision 131kHz oscillator must also be enabled via HVCFG0[6]. Setting this bit increases current consumption by approximately 50uA and should be disabled when not in use. XTAL Power Down: Cleared by the user to Power down the external crystal circuitry. Set by the user to enable the external crystal circuitry. PLL Power Down1: This bit is cleared to 0 to power down the PLL. The PLL can not be powered down if either the core or peripherals are enabled: Bits 3, 4 and 5 must be cleared simultaneously. Set by default, and set by hardware on a wake up event Peripherals2,3, 4Power Down: Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: bits 3 and 4 must be cleared simultaneously. Set by default, or and by hardware on a wake up event Core Power Down:5 Cleared to power down the ARM Core Set by default, and set by hardware on a wake up event CD Core clock divider bits: 000 20.48 MHz 48.83ns 001 10.24 MHz 97.66ns 010 5.12 MHz 195.31ns 011 2.56 MHz 390.63ns 100 1.28 MHz 781.25ns 101 640 kHz 1.56s 110 320 kHz 3.125s 111 160 kHz 6.25s
1 2
Timer peripherals will be powered down if driven from the PLL Output clock. Timers driven from an active clock source will stay in normal power mode. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE Memory and GPIO Interfaces SPI and UART Serial Ports 3 LIN can still respond to wake-up events even if this bit is cleared. 4 Wake-Up Timer (Timer2) can still be active if driven from low power oscillator even if this bit is set. 5 If user code powers down the MCU, a dummy MCU cycle should be included after the power-down command is written to POWCON.
Rev. PrD | Page 71 of 128
Preliminary Technical Data
ADUC7032 LOW POWER CLOCK CALIBRATION
The low power 131kHz oscillator may be calibrated using either the precision 131kHz oscillator, or an external 32.768KHz watch crystal. Two dedicated calibration counters and an oscillator trim register are used to implement this feature. One counter, 9-bits wide, is clocked by the accurate clock oscillator, either the Precision oscillator or external watch crystal. The second counter, 10-bits wide, is clocked by the low power oscillator, either directly at 131kHz or via a divide by 4 block generating 32.768kHz. The source for each calibration counter should be of the same frequency. The trim register (OSC0TRM) is an 8-bit wide register, the lower 4-bits of which are user accessible trim bits. Increasing the value in OSC0TRM will decrease the frequency of the low power oscillator, decreasing the value will increase the frequency. Based on a nominal frequency of 131KHz, the typical trim range is between 127KHz to 135KHz. The OSC0TRIM bits have a resolution of typically 500Hz per LSB.
ADUC7032
When the OSC0TRM has been changed the routine should be re-run and the new frequency checked. Using the internal precision 131kHz oscillator, it will take approximately 4milliseconds to execute the calibration routine. If the external 32.768kHz crystal is used, this time increases to 16milliseconds. NOTE: Prior to the clock calibration routine been started, it is required that the user switch to either the precision 131kHz oscillator or the external 32.768KHz watch crystal as the PLL Clock Source. If this is note done, it is possible that the PLL will lose lock each time OSC0TRM is modified. This will increase the length of time it takes to calibrate the Low Power, Oscillator.
BEGIN CALIBRATION ROUTINE
The clock calibration mode is configured and controlled by the following MMRs: OSC0CON: OSC0STA: OSC0VAL0: OSC0VAL1: OSC0TRM: Control bits for calibration, Calibration Status Register 9Bit counter. Counter 0 10Bit counter. Counter 1 Oscillator Trim Register
WHILE OSCSTA[0] = 1
OSC0VAL0 < OSC0VAL1
OSC0VAL0 > OSC0VAL1
OSC0VAL0 = OSC0VAL1
An example calibration routine is shown in Figure 28. User code configures and enables the calibration sequence via OSC0CON. When the precision oscillator calibration counter, OSC0VAL0, reaches 0x1FF, both counters are disabled. User code then reads back the value of the low power oscillator calibration counter. There are three possible scenarios: OSC0VAL0 = OSC0VAL1. No Further Action is required. OSC0VAL0 > OSC0VAL1. The Low Power Oscillator is running slow. OSC0TRM must be decreased. OSC0VAL0 < OSC0VAL1. The Low Power Oscillator is running fast. OSC0TRM must be increased.
INCREASE OSC0TRM
DECREASE OSC0TRM
NO
IS ERROR WITHIN DESIRED LEVEL? YES
Figure 28 : Example OSC0TRM Calibration Routine
Rev. PrD | Page 72 of 128
05994-028
END CALIBRATION ROUTINE
Preliminary Technical Data
OSC0TRM Register :
Name : Address : Default Value : Access : Function : OSC0TRM 0xFFFF042C 0x08 Read/Write This 8-bit register controls the Low Power Oscillator Trim
ADUC7032
Table 38 : OSC0TRM MMR Bit Definition
Bit 7-4 3-0
Description Reserved and should be written as zeros User Trim Bits
OSC0CON Register :
Name : Address : Default Value : Access : Function : OSC0CON 0xFFFF0440 0x00 Read/Write This 8-bit register controls the Low Power Oscillator Calibration routine
Table 39: OSC0CON MMR Bit Definition
Bit 7-5 4
Description Reserved and should be written as zeros Calibration Source Set to select external 32.768KHz crystal Cleared to select internal precision 131KHz Oscillator. Calibration Reset Set to reset the calibration counters and disable the Calibration logic Set to clear OSCVAL1 Set to clear OSCVAL0 Calibration Enable Set to begin calibration Cleared to abort calibration
3 2 1 0
Rev. PrD | Page 73 of 128
Preliminary Technical Data
OSC0STA Register :
Name : Address : Default Value : Access : Function : OSC0STA 0xFFFF0444 0x00 Read Access only This 8-bit register reflects the status of the Low Power Oscillator Calibration routine
ADUC7032
Table 40 : OSC0STA MMR Bit Definition
Bit 31-4 3-2
Description Reserved Current State of Calibration 00 Calibration Idle, device disabled or completed 01 Counter Enable state 10 Counting 11 Finished, return to Idle Calibration Enable Set to begin calibration Cleared to abort calibration Set if calibration is in progress. Cleared if calibration completed
1
0
OSC0VAL0 Register :
Name : OSC0VAL0 Address : 0xFFFF0448 Default Value : 0x00 Access : Read Access only Function : This 9-bit counter is clocked from either the 131kHz Precision Oscillator or the 32.768kHz external crystal.
OSC0VAL1 Register :
Name : OSC0VAL1 Address : 0xFFFF044C Default Value : 0x00 Access : Read Access only Function : This 10 bit counter is clocked from the Low Power, 131kHz oscillator..
Rev. PrD | Page 74 of 128
Preliminary Technical Data
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 15 interrupt sources on the ADUC7032 which are controlled by the Interrupt Controller. Most interrupts are generated from the on-chip peripherals such as the ADC, UART, etc.. The ARM7TDMI CPU core will only recognize interrupts as one of two types, a normal interrupt request IRQ and a fast interrupt request FIQ. All the interrupts can be masked separately. The control and configuration of the interrupt system is managed through nine interrupt-related registers, four dedicated to IRQ, four dedicated to FIQ. An additional MMR is used to select the programmed interrupt source. The bits in each IRQ and FIQ registers represent the same interrupt source as described in Table 41. IRQSTA/FIQSTA should be saved immediately upon entering the ISR ( Interrupt Service Routine ) to ensure that all valid interrupt sources are serviced. The interrupt generation route through the ARM7TDMI core is shown in Figure 29.
ADUC7032
Consider the example of Timer0 which is configured to generate a timeout every 1ms. After the first 1ms timeout, FIQSIG/IRQSIG[2] will be set and will only be cleared by writing to T0CLRI. If Timer0 is not enabled in either IRQEN or FIQEN, then FIQSTA/IRQSTA[2] will not be set and an interrupt will not occur. If Timer0 is enabled in either IRQEN or FIQEN, then either FIQSTA/IRQSTA[2] will be set and either an FIQ or an IRQ interrupt will occur. Please note that the IRQ and FIQ interrupt bit definitions in the CPSR only control interrupt recognition by the ARM Core, not by the peripherals. For example, if Timer2 is confirgured to generate an IRQ via IRQEN, the IRQ interrupt bit is set ( Disabled ) in the CPSR and the ADUC7032 is powered down. When an interrupt occurs, the peripherals will be woken, but the ARM core will remain powered down. This is equivalent to POWCON = 0x71. The ARM Core can only be powered up by a reset event if this occurs.
Table 41 : IRQ/FIQ MMRs bit description
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Description All interrupts OR'ed SWI: not used in IRQEN/CLR and FIQEN/CLR Timer 0 Timer 1 Timer 2 - Wake Up timer Timer 3 - Watchdog Timer Reserved and should be written as zero LIN Hardware Flash/EE Interrupt PLL Lock ADC UART SPI XIRQ0 ( GPIO IRQ 0 ) XIRQ1 ( GPIO IRQ 1 ) Reserved and should be written as zero IRQ3 High Voltage IRQ XIRQ4 XIRQ5 ( GPIO IRQ 4 ) ( GPIO IRQ 5 )
For more information please refer to:
Timer0 - Life-Time timer Page 78 Timer1 Page 79 Timer2 - Wake-Up Timer Page 82 Timer3 - Watchdog Timer Page 83 LIN (Local Interconnect Network ) INTERFACE Page 115 Flash/EE memory Control Interface Page 31 ADUC7032 System Clocks Page 68 16-Bit - Analog to Digital Converters Page 44 UART SERIAL INTERFACE Page 105 SERIAL PERIPHERAL INTERFACE Page 112 General Purpose I/O Page 84 General Purpose I/O Page 84 High Voltage Interrupt General Purpose I/O Page 84 General Purpose I/O Page 84
Rev. PrD | Page 75 of 128
Preliminary Technical Data
IRQ
The IRQ is the exception signal to enter the IRQ mode of the processor. It is used to service general purpose interrupt handling of internal and external events. The four 32-bit registers dedicated to IRQ are: - IRQSIG, reflects the status of the different IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG will be set, otherwise it is cleared. The IRQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read-only. IRQSIG may be used to poll interrupt sources. - IRQEN, provides the value of the current enable mask. When bit is set to 1, the source request is enabled to create an IRQ exception. When bit is set to 0, the source request is disabled or masked which will not create an IRQ exception. - IRQCLR, (write-only register) allows clearing the IRQEN register in order to mask an interrupt source. Each bit set to 1 will clear the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers IRQEN and IRQCLR allows independent manipulation of the enable mask without requiring an atomic read-modifywrite. - IRQSTA, (read-only register) provides the current enabled IRQ source status( effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1 that source will generate an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. All 32 bits are logically OR'ed to create a single IRQ signal to the ARM7TDMI core.
ADUC7032
FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks.
Programmed interrupts
As the programmed interrupts are non-maskable, they are controlled by another register, SWICFG, which write into both IRQSTA and IRQSIG registers or/and FIQSTA and FIQSIG registers at the same time. The 32-bit register dedicated to software interrupt is SWICFG described in Table 42a. This MMR allows the control of programmed source interrupt.
Table 42 : SWICFG MMR Bit Descriptions
Bit 31-3 2
Description Reserved Programmed Interrupt-FIQ Setting/clearing this bit correspond in setting/clearing bit 1 of FIQSTA and FIQSIG Programmed Interrupt-IRQ Setting/clearing this bit correspond in setting/clearing bit 1 of IRQSTA and IRQSIG Reserved
1
0
Note that any interrupt signal must be active for at least the minimum interrupt latency time, to be detected by the interrupt controller and to be detected by user in the IRQSTA/FIQSTA register.
TIMER0 TIMER1 TIMER2 TIMER3 LIN H/W FLASH/EE PLL LOCK ADC UART SPI XIRQ TIMER0 TIMER1 TIMER2 TIMER3 LIN H/W FLASH/EE PLL LOCK ADC UART SPI XIRQ
The FIQ (Fast Interrupt reQuest) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transferor communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface providing the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR and FIQSTA. Bit 31 to 1 of FIQSTA are logically OR'ed to create the FIQ signal to the core and the bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR will not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to `1' in FIQEN will, as a side-effect, clear the same bit in IRQEN. A bit set to `1' in IRQEN will, as a side-effect, clear the same bit in
IRQSIG FIQSIG
FIQ
IRQSTA FIQSTA
IRQ FIQ
IRQEN FIQEN
Figure 29: Interrupt Structure
Rev. PrD | Page 76 of 128
05994-029
Preliminary Technical Data
TIMERS
The ADUC7032 features four general purpose Timer/Counters: - Timer0, or Life-Time Timer - Timer1, - Timer2 or Wake-up Timer, - Timer3 or Watchdog Timer. The four timers in their normal mode of operation may either be free-running or periodic. - In free-running mode the counter decrements/increments from the maximum/minimum value until zero/full scale and starts again at the maximum /minimum value. - In periodic mode the counter decrements/increments from the value in the Load Register(TxLD MMR,) until zero/full scale and starts again at the value stored in the Load Register.
ADUC7032
The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the Control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time the value of the counter reaches zero, if counting down, or full-scale, if counting up. An IRQ can be cleared by writing any value to Clear register of the particular timer (TxCLRI). Once TxCLRI is written to, the Timer is reloaded with TxLD within 4 clocks of the timers clock source.
Table 43 : Timer Event Capture
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Description Timer 0 Timer 1 Timer 2 - Wake Up timer Timer 3 - Watchdog Timer Reserved LIN Hardware Flash/EE Interrupt PLL Lock ADC UART SPI XIRQ0 ( GPIO IRQ 0 ) XIRQ1 ( GPIO IRQ 1 ) Reserved IRQ3 High Voltage IRQ XIRQ4 XIRQ5 ( GPIO IRQ 4 ) ( GPIO IRQ 5 )
For more information please refer to: Timer0 - Life-Time timer Page 78 Timer1 Page 79 Timer2 - Wake-Up Timer Page 82 Timer3 - Watchdog Timer Page 83 Should be written as zero LIN (Local Interconnect Network ) INTERFACE Page 115 Flash/EE memory Control Interface Page 31 ADUC7032 System Clocks Page 68 16-Bit - Analog to Digital Converters Page 44 UART SERIAL INTERFACE Page 105 SERIAL PERIPHERAL INTERFACE Page 112 General Purpose I/O Page 84 General Purpose I/O Page 84 Should be written as zero High Voltage Interrupt General Purpose I/O Page 84 General Purpose I/O Page 84
Rev. PrD | Page 77 of 128
Preliminary Technical Data
TIMER0 - LIFE-TIME TIMER
Timer0 is a general purpose 48-bit count-up, or a 16-bit count up/down timer with a programmable prescalar. Timer0 may be clocked from either the Core clock, the Low Power 32.768kHz Oscillator, the Precision 32.768kHz Oscillator or an external 32.768kHz crystal, with a prescalar of 1,16, 256 or 32768. This gives a minimum resolution of 48.83ns when the core is operating at 20.48MHz, and with a prescalar of 1. In 48-bit mode, Timer0 counts up from zero. The current counter value may be read from T0VAL0 and T0VAL1. In 16-Bit mode,Timer0 may count up or count down. A 16-bit value may be written to T0LD which will be loaded into the counter. The current counter value may be read from T0VAL0. Timer0 has a capture register (T0CAP), which may be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone.
ADUC7032
Timer0 reloads the value from T0LD either when TIMER0 overflows, or immediately when T0CLRI is written. Timer0 interface consists of six MMRS: - T0LD is a 16-bit register which holds the 16 bit value that is loaded into the counter. Only available in 16-bit mode. - T0CAP is a 16-bit register which holds the 16-bit value captured by an enabled IRQ event. Only available in 16-bit mode. - T0VAL0/T0VAL1 are 16-bit and 32-bit registers which hold the 16 least significant bits and 32 most significant bits respectively. T0VAL0 and T0VAL1 is read-only. In 16-bit mode 16-bit T0VAL0 is used. In 48-bit mode both 16-bit T0VAL0 and 32-bit T0VAL1 are used. - T0CLRI is an 8-bit register. Writing any value to this register will clear the interrupt. Only available in 16-bit mode. - T0CON is the configuration MMR described in Table 44.
LOW POWER 32.768kHz OSCILLATOR PRECISION 32.768kHz OSCILLATOR EXTERNAL 32.768kHz WATCH CRYSTAL CORE CLOCK FREQUENCY PRESCALER 1, 16, 256, OR 32768
16-BIT LOAD
48-BIT UP COUNTER 16-BIT UP/DOWN COUNTER
TIMER0 IRQ
TIMER0 VALUE IRQ[31:0] CAPTURE
05994-030
Figure 30 : Timer 0 block diagram
Timer0 Value Register :
Name : T0VAL0/T0VAL1 Address : 0xFFFF0304, 0xFFFF0308 Default Value : 0x00, 0x00 Access : Read Only Function : T0VAL0 and T0VAL1 are 16-bit and 32-bit registers which hold the 16 least significant bits and 32 most significant bits respectively. T0VAL0 and T0VAL1 is read-only. In 16-bit mode 16-bit T0VAL0 is used. In 48-bit mode both 16bit T0VAL0 and 32-bit T0VAL1 are used.
Timer0 Capture Register :
Name : T0CAP Address : 0xFFFF0314 Default Value : 0x00 Access : Read Only Function : This is a 16-bit register which holds the 16bit value captured by an enabled IRQ event. Only available in 16-bit mode.
Rev. PrD | Page 78 of 128
Preliminary Technical Data
Timer0 Control Register :
Name : Address : Default Value : Access : Function : T0CON 0xFFFF030C 0x00 Read/Write Only The 17-bit MMR configures the mode of operation of Timer0
ADUC7032
Table 44 : T0CON MMR Bit Descriptions
Bit 31-18 17
Description Reserved This bit is reserved and should be written as 0 by user code. Event Select bit: Set by user to enable time capture of an event Cleared by user to disable time capture of an event Event select range, 0 to 31 The events are as described in Table 43. Reserved This bit is reserved and should be written as 0 by user code. Clock Select: 00 Core Clock ( Default ) 01 Low Power 32.768kHz Oscillator 10 External 32.768kHz Watch Crystal 11 Precision 32.768kHz Oscillator Count up: ( Only available in 16Bit Mode ) Set by user for timer 0 to count up Cleared by user for timer 0 to count down. ( Default ) Timer0 enable bit: Set by user to enable timer 0 Cleared by user to disable timer 0. ( Default ) Timer 0 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Reserved This bit is reserved and should be written as 0 by user code. Timer0 Mode of Operation: 0 16 Bit operation ( Default ) 1 48 Bit Operation Prescalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 1111 Source clock / 32768
16-12 11 10-9
8
7
6
5 4
3-0
Timer0 Load Registers:
Name : T0LD Address : 0xFFFF0300 Default Value : 0x00 Access : Write Once Only Function : T0LD0 is a 16-bit register which holds the 16 bit value that is loaded into the counter. Only available in 16-bit mode.
Timer0 Clear Register :
Name : T0CLRI Address : 0xFFFF0310 Default Value : 0x0FF Access : Write Only Function : This 16-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer0.
Rev. PrD | Page 79 of 128
Preliminary Technical Data
TIMER1
Timer1 is a 32-bit general purpose timer, count-down or countup, with a programmable pre-scalar. The pre-scalar source can be the Low Power 32.768kHz Oscillator, the core clock, or from one of two external GPIO. This source can be scaled by a factor of 1, 16, 256 or 32768. This gives a minimum resolution of 48.83ns when operating at CD zero, the core is operating at 20.48MHz, and with a pre-scalar of 1 ( Ignoring external GPIO). The counter can be formatted as a standard 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer1 has a capture register (T1CAP), which can be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Timer1 interface consists of five MMRS: - T1LD, T1VAL and T1CAP are 32-bit registers and hold 32bit unsigned integers. T1VAL and T1CAP are read-only. - T1CLRI is an 8-bit register. Writing any value to this register will clear the timer1 interrupt. - T1CON is the configuration MMR described in below. Timer1 features a post-scalar. This allows the user to count between1 and 256 the number of timer1 timeouts. To activate the post-scalar, the user sets bit 23 and writes the desired number to count into bits 24-31 of T1CON. Once that number of timeouts has reached, Timer1 will generate an interrupt if T1CON[18] is set. NOTE:
ADUC7032
If the part is in a low power mode, and Timer1 is clocked from the GPIO or low power oscillator source then, Timer1 will continue to be operate.
Timer1 reloads the value from T1LD either when TIMER01 overflows, or immediately when T1CLRI is written.
Timer1 Load Registers:
Name : T1LD Address : 0xFFFF0320 Default Value : 0x00000 Access : Write Only Function : T1LD is a 32 bit register which holds the 32 bit value that is loaded into the counter.
Timer1 Clear Register :
Name : T1CLRI Address : 0xFFFF032C Default Value : 0xFF Access : Write Only Function : This 32-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer1.
Timer1 Value Register :
Name : T1VAL Address : 0xFFFF0324 Default Value : 0xFFFFFFFF Access : Read Only Function : T1VAL is a 32-bit register which holds the current value of Timer1
32-BIT LOAD LOW POWER 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY GPIO GPIO TIMER1 VALUE IRQ[31:0] CAPTURE
05994-031
PRESCALER 1, 16, 256, OR 32768
32-BIT UP/DOWN COUNTER
8-BIT POSTSCALER
TIMER1 IRQ
Figure 31 : Timer 1 Block Diagram
Rev. PrD | Page 80 of 128
Preliminary Technical Data
Timer1 Capture Register :
Name : T1CAP Address : 0xFFFF0330 Default Value : 0x00 Access : Write Only Function : This is a 32-bit register which holds the 32bit value captured by an enabled IRQ event.
ADUC7032
Timer1 Control Register :
Name : T1CON Address : 0xFFFF0328 Default Value : 0x0000 Access : Read/Write Only Function : This 32-bit MMR configures the mode of operation of Timer1
Table 45 : T1CON MMR Bit Descriptions
Bit 31-24
Description Timer 1 8 Bit Post-Scalar By writing to these 8 bits, a value is loaded into the post-scalar. By reading these 8 bits, the current value of the counter is loaded. Timer 1 Enable Post-Scalar: Set To enable Timer1 Post Scalar. If enabled, an interrupts will be generated after T1CON[31-24] periods as defined by T1LD. Cleared To disable Timer1 Post Scalar. Reserved This bit is reserved and should be written as 0 by user code. Post-Scalar Compare Flag. Set if the number of Timer1 overflows is equal to the number written to the post-scalar Timer 1 Interrupt Source Set To select interrupt generation from post-scalar counter Cleared To select interrupt generation direct from Timer1 Event Select bit: Set by user to enable time capture of an event Cleared by user to disable time capture of an event Event select range, 0 to 31 The events are as described in Table 43. Clock select: 000 Core clock ( Default ) 001 Low Power 32.768kHz Oscillator 010 GPIO8 011 GPIO5 Count up: Set by user for timer 1 to count up Cleared by user for timer 1 to count down. ( Default ) Timer1 enable bit: Set by user to enable timer 1 Cleared by user to disable timer 1. ( Default ) Timer 1 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Format: 00 Binary ( Default ) 01 Reserved 10 Hr:Min:Sec:Hundredths - 23 hours to 0 hour 11 Hr:Min:Sec:Hundredths - 255 hours to 0 hour Pre-Scalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 1111 Source clock / 32768
23
22-20 19 18
17
16-12 11-9
8
7
6
5-4
3-0
Rev. PrD | Page 81 of 128
Preliminary Technical Data
TIMER2 - WAKE-UP TIMER
Timer2 is a 32-bit wake-up timer, count-down or count-up, with a programmable prescalar. The pre-scalar is clocked directly from 1 of 4 clock sources, namely, the Core Clock (default selection), the Low Power 32.768kHz Oscillator, External 32.768kHz Watch Crystal, or the Precision 32.768kHz Oscillator. The selected clock source can be scaled by a factor of 1, 16, 256 or 32768. The wake-up timer will continue to run when the core clock is disabled. This gives a minimum resolution of 48.83ns when operating at CD zero, the core is operating at 20.48MHz, and with a prescalar of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4]. The counter can be formatted as plain 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer2 reloads the value from T2LD either when TIMER2 overflows, or immediately when T2CLRI is written. Timer2 interface consists of four MMRS: - T2LD and T2VAL are 32-bit registers and hold 32-bit unsigned integers. T2VAL is read-only. - T2CLRI is an 8-bit register. Writing any value to this register will clear the timer2 interrupt. - T2CON is the configuration MMR described in Table 36 below.
ADUC7032
Timer2 Load Registers:
Name : T2LD Address : 0xFFFF0340 Default Value : 0x00000 Access : Write Only Function : T2LD is a 32 bit register which holds the 32 bit value that is loaded into the counter.
Timer2 Clear Register :
Name : T2CLRI Address : 0xFFFF034C Default Value : 0xFF Access : Write Only Function : This 32-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer2.
Timer2 Value Register :
Name : T2VAL Address : 0xFFFF0344 Default Value : 0xFFFFFFFF Access : Read Only Function : T2VAL is a 32-bit register which holds the current value of Timer2
PRECISION 32.768kHz OSCILLATOR LOW POWER 32.768kHz OSCILLATOR CORE CLOCK EXTERNAL 32.768kHz WATCH CRYSTAL PRESCALER 1, 16, 256, OR 32768
32-BIT LOAD
32-BIT UP/DOWN COUNTER
TIMER2 IRQ
TIMER2 VALUE
Figure 32 : Timer 2 block diagram
Rev. PrD | Page 82 of 128
05994-032
Preliminary Technical Data
Timer2 Control Register :
Name : Address : Default Value : Access : Function : T2CON 0xFFFF0348 0x0000 Read/Write Only This 32-bit MMR configures the mode of operation of Timer2
Table 46 : T2CON MMR Bit Descriptions
ADUC7032
Bit 31-11 10-9
Description Reserved Clock Source Select: 00 Core Clock ( Default ) 01 Low Power 32.768kHz Oscillator 10 External 32.768kHz Watch Crystal 11 Precision 32.768kHz Oscillator Count up: Set by user for timer 2 to count up Cleared by user for timer 2 to count down. ( Default ) Timer2 enable bit: Set by user to enable timer 2 Cleared by user to disable timer 2. ( Default ) Timer 2 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Format: 00 Binary ( Default ) Reserved 01 10 Hr:Min:Sec:Hundredths - 23 hours to 0 hour 11 Hr:Min:Sec:Hundredths - 255 hours to 0 hour Prescalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 ( This setting should be used in conjunction Timer2 Formats 1,0 and 1,1 ) 1111 Source clock / 32768
8
7
6
5-4
3-0
Rev. PrD | Page 83 of 128
Preliminary Technical Data
TIMER3 - WATCHDOG TIMER
Timer3 has two modes of operation, normal mode and watchdog mode. The Watchdog timer is used to recover from an illegal software state. Once enabled it requires periodic servicing to prevent it from forcing a reset of the processor. Timer3 reloads the value from T3LD either when TIMER3 overflows, or immediately when T3CLRI is written.
ADUC7032
User software should only configure a minimum timeout period of 30msecs. This is to avoid any conflict with Flash/EE memory page erase cycles, which require 20ms to complete a single page erase cycle. If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value must be written to T3ICLR before T3VAL reaches zero. This reloads the counter with T3LD and begins a new timeout period. Once watchdog mode is entered, T3LD and T3CON are writeprotected. These two registers can not be modified until a reset event resets the Watchdog Timer. Timer3 is automatically halted during JTAG debug access and will only recommence counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This may be disabled by setting bit zero in T3CON. It is recommended that the default value is used, i.e. that the Watchdog Timer continues to count during power-down.
Normal mode:
The Timer3 in normal mode is identical to Timer0, in 16-bit mode of operation, except for the clock source. The clock source is the Low Power 32.768kHz oscillator and can be scaled by a factor of 1, 16, or 256. Timer3 also features a capture facility, which allows the capture of the current timer value if the Timer2 interrupt is enabled via IRQEN[5].
Watchdog mode:
Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in T3LD Register until zero. The maximum timeout is 512 seconds, using the maximum pre-scalar /256 and full-scale in T3LD.
16-BIT LOAD
LOW POWER 32.768kHz
PRESCALER 1, 16, 256
16-BIT UP/DOWN COUNTER
WATCHDOG RESET TIMER3 IRQ
TIMER3 VALUE
Figure 33 : Timer3 Block Diagram
Timer3 Interface:
Timer3 interface consists of four MMRS: - T3CON is the configuration MMR described in Table 37 - T3LD and T3VAL are 16-bit registers (bit 0 to 15) and hold 16-bit unsigned integers. T3VAL is read-only. - T3CLRI is an 8-bit register. Writing any value to this register will clear the Timer3 interrupt in normal mode or will reset a new timeout period in watchdog mode
Timer3 Load Register :
Name : Address : Default Value : Access : Function : value. T3LD 0xFFFF0364 0x03D7 Write Once Only This 16-bit MMR holds the Timer3 reload
Timer3 Value Register :
Name : T3VAL Address : 0xFFFF0364 Default Value : 0x03D7 Access : Read Only Function : This 16-bit, read-only MMR holds the currentTimer3 count value.
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05994-033
Preliminary Technical Data
Timer3 Clear Register :
Name : Address : Default Value : Access : Function : T3CLRI 0xFFFF036C 0x00 Write Only This 16-bit, write-only MMR is written
ADUC7032
(with any value) by user code to refresh(reload) Timer3 in watchdog mode to prevent a watchdog timer reset event. This register must be written with a specific value (generated by user code, based on a polynomial equation) to refresh the watchdog timer and prevent a watchdog reset.
Timer3 Control Register :
Name : Address : Default Value : Access : Function : T3CON 0xFFFF0368 0x00 Read/Write Once Only The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 47.
Table 47 : T3CON MMR Bit Definition
Bit 16-9 8
Description These bits are reserved and should be written as 0 by user code Count Up/Down Enable Set by user code to configure Timer3 to count up Cleared by user code to configure Timer3 to count down.
7
Timer3 Enable Set by user code to enable Timer 3 Cleared by user code to disable Timer 3. .
6
Timer3 Operating Mode Set by user code to configure Timer3 to operate in periodic mode Cleared by user to configure Timer3 to operate in free-running mode.
5
Watchdog Timer Mode Enable Set by user code to enable watchdog mode Cleared by user code to disable watchdog mode. This bit is reserved and should be written as 0 by user code Timer3 Clock(32.768kHz) Pre-Scalar 00 Source clock / 1 ( Default ) 01 Source clock / 16 10 Source clock / 256 11 Reserved Watchdog Timer IRQ Enable Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0 Cleared by user code to disable the IRQ option.
4 3-2
1
0
PD_OFF Set by the user code to stop Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR. Cleared by the user code to enable Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
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Preliminary Technical Data
GENERAL PURPOSE I/O
The ADUC7032 features 9 General Purpose bi-directional I/O pins (GPIO). In general, many of the GPIO pins have multiple functions which can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull up resistor and their sink capability is 0.8mA and they can source 0.1mA. The 9 GPIO are grouped into three ports, Port0, Port1 and Port2. Port0 is 5 bits wide. Port1 and Port2 are both 2 bits wide. The GPIO assignment within each port is detailed in Table 48. A typical GPIO structure is shown Figure 34. External Interrupts are present on GP0, GP5, GP7 and GP8. This interrupts are level triggered and are active high. These interrupts are not latched, therefore the interrupts source must be present until either IRQSTA or FIQSTA are interrogated. The Interrupt source must be active for at least 1 CD divided core clock to guarantee recognition.
ADUC7032
All port pins are configured and controlled by 4 sets (1 set for each port) of four port specific MMRs: GPxCON: Port x Control Register GPxDAT: Port x Configuration and Data Register GPxSET: Data set port x GPxCLR: Data clear port x where x corresponds to the port number 0,1 or 2 During normal operation, user code can control the function and state of the external GPIO pins via these general purpose registers. All GPIO pins will retain their external (high or low) during power-down (POWCON) mode.
OUTPUT DRIVE ENABLE GPxDAT[31:24] OUTPUT DATA GPxDAT[23:16] INPUT DATA GPxDAT[7:0]
REG_DVDD
GPIO
1ONLY
AVAILABLE ON GP0, GP5, GP7, AND GP8.
Figure 34 : ADUC7032 GPIO
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05994-035
GPIO IRQ1
Preliminary Technical Data
Table 48 : External GPIO Pin to Internal Port Signal Assignments
ADUC7032
GPIO PIN GPIO0
PORT SIGNAL P0.0 IRQ0
Functionality ( Defined by GPxCON ) General Purpose I/O SS, Slave Select I/O for SPI General Purpose I/O SCLK, Serial Clock I/O for SPI General Purpose I/O MISO, Master Input, Slave Output for SPI General Purpose I/O MOSI, Master Output, Slave Input for SPI General Purpose I/O ECLK , a 2.56MHz clock output
GPIO1 GPIO2 GPIO3 GPIO4
P0.1 P0.2 P0.3 P0.4 P0.5
1 1
Port 0
High Voltage Serial Interface High Voltage Serial Interface General Purpose I/O RxD Pin for UART General Purpose I/O TxD Pin for UART General Purpose I/O LIN Output Pin. Used to read directly from LIN PIN for conformance testing. General Purpose I/O LIN HV Input Pin. Used to directly drive LIN Pin for conformance testing. General Purpose I/O LIN Output Pin General Purpose I/O LIN Input Pin Reserved Reserved
P0.6 GPIO5 P1.0
Port 1
IRQ1 GPIO6 GPIO7 GPIO8 GPIO11 GPIO12
2
P1.1 P2.0 IRQ4 P2.1 IRQ5 P2.4 P2.5
2
2
2
Port 2
GPIO13
1
P2.6
1
These signals are internal signals only and do not appear on an external pin. These pins are used along with HVCON as the 2 wire interface to the high voltage interface circuits. 2 These pins/signals are internal signals only and do not appear on an external pins. Both signals are used to provide external pin diagnostic write(GPIO12) and read-back(GPIO11) capability.
1
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Preliminary Technical Data
GPIO Port0 Control Register :
Name : Address : Default Value : Access : Function : GP0CON 0xFFFF0D00 0x00000000 Read/Write The 32-bit MMR selects the pin function for each Port0 pin.
Table 49 : GP0CON MMR Bit Designations
ADUC7032
Bit 31-29 28 27-25 24
Description Reserved These bits are reserved and should be written as 0 by user code Reserved This bit is reserved and should be written as 1 by user code Reserved These bits are reserved and should be written as 0 by user code Internal P0.6 Enable Bit This bit must be set to 1 by user software to enable the High Voltage Serial Interface before using the HVCON and HVDAT registered high voltage interface
23-21 20
Reserved These bits are reserved and should be written as 0 by user code Internal P0.5 Enable Bit This bit must be set to 1 by user software to enable the High Voltage Serial Interface before using the HVCON and HVDAT registered high voltage interface
19-17 16
Reserved These bits are reserved and should be written as 0 by user code GPIO4 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO4 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO4 pin as ECLK enabling a 2.56MHz clock output on this pin Reserved These bits are reserved and should be written as 0 by user code GPIO3 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO3 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO2 pin as MOSI, Master Output, Slave Input Data for the SPI Port Reserved These bits are reserved and should be written as 0 by user code GPIO2 Function Select Bit This bit is cleared to 0 by user code to configure the GPIO2 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO3 pin as MISO, Master Input, Slave Output Data for the SPI Port Reserved These bits are reserved and should be written as 0 by user code GPIO1 Function Select Bit This bit is cleared to 0 by user code to configure the GPIO1 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO1 pin as SCLK, Serial Clock I/O for the SPI Port Reserved These bits are reserved and should be written as 0 by user code GPIO0 Function Select Bit This bit is cleared to 0 by user code to configure the GPIO0 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO0 pin as SS, Slave Select I/O for the SPI Port
15-13 12
11-9 8
7-5 4
3-1 0
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Preliminary Technical Data
GPIO Port1 Control Register :
Name : Address : Default Value : Access : Function : GP1CON 0xFFFF0D04 0x00000000 Read/Write The 32-bit MMR selects the pin function for each Port1 pin.
ADUC7032
Table 50 : GP1CON MMR Bit Designations
Bit 31-5 4
Description Reserved These bits are reserved and should be written as 0 by user code GPIO6 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO6 pin as a General Purpose I/O (GPIO) pin This bit is set to 1 by user code to configure the GPIO6 pin as TxD, Transmit Data for UART Serial Port Reserved These bits are reserved and should be written as 0 by user code GPIO5 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO5 pin as a General Purpose I/O (GPIO) pin This bit is set by user code to 1 to configure the GPIO5 RxD. Receive Data for UART Serial Port
3-1 0
GPIO Port2 Control Register :
Name : Address : Default Value : Access : Function : GP2CON 0xFFFF0D08 0x00000000 Read/Write The 32-bit MMR selects the pin function for each Port2 pin.
Table 51 : GP2CON MMR Bit Designations
Bit 31-21 20
Description Reserved These bits are reserved and should be written as 0 by user code GPIO12 Function Select Bit This bit is cleared to 0 by user code to route the LIN transmit data to an internal General Purpose I/O (GPIO12) pad which can then be written via the GP2DAT MMR. This bit is set to 1 by user code to route the UART TxD (transmit data) to the LIN data pin. This configuration is used in LIN mode.
19-17
Reserved These bits are reserved and should be written as 0 by user code
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Preliminary Technical Data
16 GPIO11 Function Select Bit
ADUC7032
This bit is cleared to 0 by user code to internally disable the LIN input data path. In this configuration GPIO11 is used to support diagnostic read-back on all external high-voltage I/O pins (see HVCFG1[2:0]) This bit is set to 1 by user code to route input data from the LIN interface to both the LIN hardware timing/synchronization logic and to the UART RxD (receive data). This mode must be configured by user code when using LIN . 15-5 4 Reserved These bits are reserved and should be written as 0 by user code GPIO8 Function Select Bit This bit is cleared by user code to 0 to configure the GPIO8 pin as a General Purpose I/O (GPIO) pin This bit is set by user code to 1 to route the LIN input data to the GPIO8 pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU or UART. 3-1 0 Reserved These bits are reserved and should be written as 0 by user code GPIO7 Function Select Bi This bit is cleared by user code to 0 to configure the GPIO7 pin as a General Purpose I/O (GPIO) pin This bit is set by user code to 1 to route data driven into the GPIO7 pin through the on-chip LIN transceiver to be output at the LIN pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU or UART.
GPIO Port0 Data Register :
Name : Address : Default Value : Access : Function : GP0DAT 0xFFFF0D20 0x00000000 Read/Write This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 48). This register also sets the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Table 52 : GP0DAT MMR Bit Descriptions
Bit 31-29 28
Description Reserved These bits are reserved and should be written as 0 by user code Port 0.4 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.4 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.4 as an output. Port 0.3 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.3 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.3 as an output. Port 0.2 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.2 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.2 as an output. Port 0.1 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.1 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.1 as an output. Port 0.0 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P0.0 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P0.0 as an output. Reserved These bits are reserved and should be written as 0 by user code
27
26
25
24
23-21
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Preliminary Technical Data
20 19 18 17 16 15-5 4 3 2 1 0
ADUC7032
Port 0.4 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.4. Port 0.3 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.3. Port 0.2 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.2. Port 0.1 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.1. Port 0.0 Data Output The value written to this bit appears directly on the GPIO pin assigned to P0.0. Reserved These bits are reserved and should be written as 0 by user code Port 0.4 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.4. User code should write 0 to this bit. Port 0.3 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.3. User code should write 0 to this bit. Port 0.2 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.2. User code should write 0 to this bit. Port 0.1 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.1. User code should write 0 to this bit. Port 0.0 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P0.0. User code should write 0 to this bit.
GPIO Port1 Data Register :
Name : Address : Default Value : Access : Function : GP1DAT 0xFFFF0D30 0x00000000 Read/Write This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 48). This register also sets the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Table 53 : GP1DAT MMR Bit Descriptions
Bit 31-26 25
Description Reserved These bits are reserved and should be written as 0 by user code Port 1.1 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P1.1 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P1.1 as an output. Port 1.0 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P1.0 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P1.0 as an output. Reserved These bits are reserved and should be written as 0 by user code Port 1.1 Data Output The value written to this bit appears directly on the GPIO pin assigned to P1.1. Port 1.0 Data Output The value written to this bit appears directly on the GPIO pin assigned to P1.0. Reserved These bits are reserved and should be written as 0 by user code Port 1.1 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P1.1. User code should write 0 to this bit. Port 1.0 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P1.0. User code should write 0 to this bit.
24
23-18 17 16 15-2 1 0
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Preliminary Technical Data
GPIO Port2 Data Register :
Name : Address : Default Value : Access : Function : GP2DAT 0xFFFF0D40 0x00000000 Read/Write
ADUC7032
This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 48). This register also sets the output value for GPIO pins configured as outputs and reads the status of GPIO pins configured as inputs.
Table 54 :GP2DAT MMR Bit Descriptions
Bit 31 30
Description Reserved This bit is reserved and should be written as 0 by user code Port 2.6 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.6 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.6 as an output.
29
Port 2.5 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.5 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.5 as an output. This configuration is used to support diagnostic write capability to the high-voltage I/O pins.
28
Port 2.4 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.4 as an input. This configuration is used to support diagnostic read-back capability from the high-voltage I/O pins(see HVCFG1[2:0]). This bit is set to 1 by user code to configure the GPIO pin assigned to P2.4 as an output.
27-26 25
Reserved These bits are reserved and should be written as 0 by user code Port 2.1 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.1 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.1 as an output. Port 2.0 Direction Select Bit This bit is cleared to 0 by user code to configure the GPIO pin assigned to P2.0 as an input. This bit is set to 1 by user code to configure the GPIO pin assigned to P2.0 as an output. Reserved This bit is reserved and should be written as 0 by user code Port 2.6 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.6 Port 2.5 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.5. Reserved These bits are reserved and should be written as 0 by user code Port 2.1 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.1. Port 2.0 Data Output The value written to this bit appears directly on the GPIO pin assigned to P2.0. Reserved These bits are reserved and should be written as 0 by user code Port 2.6 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.6. User code should write 0 to this bit. Port 2.5 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.5. User code should write 0 to this bit. Port 2.4 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.4. User code should write 0 to this bit. Reserved These bits are reserved and should be written as 0 by user code
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24
23 22 21 20-18 17 16 15-7 6 5 4 3-2
Preliminary Technical Data
1 0
ADUC7032
Port 2.1 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.1. User code should write 0 to this bit. Port 2.0 Data Input This bit is a read-only bit that reflects the current status of the GPIO pin assigned to P2.0. User code should write 0 to this bit.
GPIO Port0 Set Register :
Name : Address : Default Value : Access : Function : GP0SET 0xFFFF0D24 0x00000000 Read/Write This 32-bit MMR allow user code to individually bit address external GPIO pins to set them high only. User code can do this via the GP0SET MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP0DAT.
Table 55 : GP0SET MMR Bit Descriptions
Bit 31-21 20
Description Reserved These bits are reserved and should be written as 0 by user code Port 0.4 Set Bit This bit is set to 1 by user code to set the external GPIO4 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO4 pin. Port 0.3 Set Bit This bit is set to 1 by user code to set the external GPIO3 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO3 pin. Port 0.2 Set Bit This bit is set to 1 by user code to set the external GPIO2 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO2 pin. Port 0.1 Set Bit This bit is set to 1 by user code to set the external GPIO1 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO1 pin. Port 0.0 Set Bit This bit is set to 1 by user code to set the external GPIO0 pin high If user software clears this bit to 0, this will have no effect on the external GPIO0 pin. Reserved These bits are reserved and should be written as 0 by user code
19
18
17
16
15-0
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Preliminary Technical Data
GPIO Port1 Set Register :
Name : Address : Default Value : Access : Function :
ADUC7032
GP1SET 0xFFFF0D34 0x00000000 Read/Write This 32-bit MMR allow user code to individually bit address external GPIO pins to set them high only. User code can do this via the GP1SET MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP1DAT.
Table 56 : GP1SET MMR Bit Descriptions
Bit 31-18 17
Description Reserved These bits are reserved and should be written as 0 by user code Port 1.1 Set Bit This bit is set to 1 by user code to set the external GPIO6 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO6 pin. Port 1.0 Set Bit This bit is set to 1 by user code to set the external GPIO5 pin high If user software clears this bit to 0, this will have no effect on the external GPIO5 pin. Reserved These bits are reserved and should be written as 0 by user code
16
15-0
GPIO Port2 Set Register :
Name : Address : Default Value : Access : Function : GP2SET 0xFFFF0D44 0x00000000 Read/Write This 32-bit MMR allow user code to individually bit address external GPIO pins to set them high only. User code can do this via the GP2SET MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP2DAT.
Table 57 : GP2SET MMR Bit Descriptions
Bit 31-23 22
Description Reserved These bits are reserved and should be written as 0 by user code Port 2.6 Set Bit This bit is set to 1 by user code to set the external GPIO13 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO13 pin. Port 2.5 Set Bit This bit is set to 1 by user code to set the external GPIO12 pin high If user software clears this bit to 0, this will have no effect on the external GPIO12 pin. Reserved These bits are reserved and should be written as 0 by user code Port 2.1 Set Bit This bit is set to 1 by user code to set the external GPIO8 pin high. If user software clears this bit to 0, this will have no effect on the external GPIO8 pin. Port 2.0 Set Bit This bit is set to 1 by user code to set the external GPIO7 pin high If user software clears this bit to 0, this will have no effect on the external GPIO7 pin. Reserved These bits are reserved and should be written as 0 by user code
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21
20-18 17
16
15-0
Preliminary Technical Data
GPIO Port0 Clear Register :
Name : Address : Default Value : Access : Function :
ADUC7032
GP0CLR 0xFFFF0D28 0x00000000 Read/Write This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only. User code can do this via the GP0CLR MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP0DAT.
Table 58 : GP0CLR MMR Bit Descriptions
Bit 31-21 20
Description Reserved These bits are reserved and should be written as 0 by user code Port 0.4 Clear Bit This bit is set to 1 by user code to clear the external GPIO4 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO4 pin. Port 0.3 Clear Bit This bit is set to 1 by user code to clear the external GPIO3 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO3 pin. Port 0.2 Clear Bit This bit is set to 1 by user code to clear the external GPIO2 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO2 pin. Port 0.1 Clear Bit This bit is set to 1 by user code to clear the external GPIO1 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO1 pin. Port 0.0 Clear Bit This bit is set to 1 by user code to clear the external GPIO0 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO0 pin. Reserved These bits are reserved and should be written as 0 by user code
19
18
17
16
15-0
GPIO Port1 Clear Register :
Name : Address : Default Value : Access : Function : GP1CLR 0xFFFF0D38 0x00000000 Read/Write This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only. User code can do this via the GP1CLR MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP1DAT.
Table 59 : GP1CLR MMR Bit Descriptions
Bit 31-18 17
Description Reserved These bits are reserved and should be written as 0 by user code Port 1.1 Clear Bit This bit is set to 1 by user code to clear the external GPIO6 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO6 pin. Port 1.0 Clear Bit This bit is set to 1 by user code to clear the external GPIO5 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO5 pin. Reserved These bits are reserved and should be written as 0 by user code
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16
15-0
Preliminary Technical Data
GPIO Port2 Clear Register :
Name : Address : Default Value : Access : Function : GP2CLR 0xFFFF0D48 0x00000000 Read/Write
ADUC7032
This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only. User code can do this via the GP2CLR MMR without having to modify or maintain the status of any other GPIO pins as user code would need to do when using GP2DAT.
Table 60 : GP2CLR MMR Bit Descriptions
Bit 31-23 22
Description Reserved These bits are reserved and should be written as 0 by user code Port 2.6 Clear Bit This bit is set to 1 by user code to clear the external GPIO13 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO8 pin. Port 2.5 Clear Bit This bit is set to 1 by user code to clear the external GPIO12 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO7 pin. Reserved These bits are reserved and should be written as 0 by user code Port 2.1 Clear Bit This bit is set to 1 by user code to clear the external GPIO8 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO8 pin. Port 2.0 Clear Bit This bit is set to 1 by user code to clear the external GPIO7 pin low. If user software clears this bit to 0, this will have no effect on the external GPIO7 pin. Reserved These bits are reserved and should be written as 0 by user code
21
20-18 17
16
15-0
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Preliminary Technical Data
HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE
The ADUC7032 integrates a number of high voltage circuit functions which are controlled and monitored via a registered interface consisting of 2 MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command byte interpreter allowing the microcontroller to indirectly read or write 8-bit data(the value in HVDAT) from/to one of 4 High voltage status/configuration registers. It should be noted that these high voltage registers are not MMRs but are so called `indirect' registers that can only be accessed (as the name suggests) indirectly via the HVCON and HVDAT MMRs. The physical interface between the HVCON register and the indirect high voltage registers is a 2 wire (data and clock) serial interface based on a 2.56MHz serial clock. Therefore, there is a finite, 10usecs(maximum) latency between the MCU core writing a command into HVCON and that command or data
ADUC7032
reaching the indirect high voltage registers. There is also a finite 10usecs latency between the MCU core writing a command into HVCON and indirect register data being read back into the HVDAT register. A busy bit (Bit0 of the HVCON when read by MCU) can be polled by the MCU to confirm when a read/write command has completed. The following high voltage circuit functions are controlled and monitored via this interface and Figure 35 below describes the top-level architecture of the high voltage interface and related circuits. - Precision Oscillator - Wake-Up pin functionality - Power Supply Monitor - Low Voltage Flag - LIN Operating Modes - High Voltage Diagnostics - High Voltage Attenuator/Buffer Circuit - High Voltage Temperature Monitor
(INDIRECT) HIGH-VOLTAGE REGISTERS
HIGH-VOLTAGE INTERFACE MMRs HVCON HVDAT
SERIAL DATA SERIAL CLOCK SERIAL INTERFACE CONTROLLER
HVCFG0 HVCFG1
HVCFG0[6]
PRECISION OSCILLATOR
HVCFG0[3] HVSTA HVMON HVCFG0[2]
PSM
LVF
PSM--HVSTA[5] IRQ3 (IRQEN[16]) WU--HVSTA[4] HIGH VOLTAGE INTERRUPT CONTROLLER OVER TEMP--HVSTA[3] LIN S-SCT--HVSTA[2] STI S-SCT--HVSTA[1] WU S-SCT--HVSTA[0] HVCFG0[5] HVCFG0[1:0] WU DIAGNOSTIC I/P HVCFG0[4] STI DIAGNOSTIC I/P P2.6 LIN DIAGNOSTIC I/P P2.5 HVCFG1[3] HVCFG1[6] HVCFG1[7] HVCFG1[5] HVCFG1[3]
05994-036
ARM7 MCU AND PERIPHERALS
LIN MODES
WU DIAGNOSTIC O/P HVMON[7] HIGH VOLTAGE DIAGNOSTIC CONTROLLER STI DIAGNOSTIC O/P HVMON[5] LIN DIAGNOSTIC O/P P2.4
HVCFG0[4] HVCFG1[4]
WU I/O CONTROL
HVCFG1[4]
STI I/O CONTROL
ATTENUATOR AND BUFFER
HV TEMP MONITOR
Figure 35 : High Voltage Interface, Top Level Block Diagram
Rev. PrD | Page 97 of 128
Preliminary Technical Data
High Voltage Interface Control Register :
Name : Address : Default Value : Access : Function : HVCON 0xFFFF0804 0x00 Read/Write
ADUC7032
This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this register are interpreted as read or write commands to a set of 4 indirect registers related to the high voltage circuits. The HVDAT register is used to store data to be written to or read back from the indirect registers
Table 61: HVCON MMR Write Bit Designations
Bit 7-0
Description Command Byte 0x00 0x01 0x02 0x03 0x08 0x09 Interpreted as Read back high voltage register HVCFG0 into HVDAT Read back high voltage register HVCFG1 into HVDAT Read back high voltage status register HVSTA into HVDAT Read back high voltage status register HVMON into HVDAT Write the value in HVDAT to the high voltage register HVCFG0 Write the value in HVDAT to the high voltage register HVCFG1
All other command bytes are reserved and should not be written by user code
Table 62: HVCON MMR Read Bit Designations
Bit 7-3 2
Description Reserved Transmit Command to High Voltage Die Status: 1 0 Command Completed Successfully Command Failed
1
Read Command from High Voltage Die Status: 1 0 Command Completed Successfully Command Failed
0
Bit 0 (Read Only) BUSY Bit When user code reads this register, Bit0 should be interpreted as the BUSY signal for the high-voltage interface. This bit can be used to determine if a read request has completed. High voltage (read/write) commands as described above should not be written to HVCON unless BUSY=0. BUSY = 1, High voltage interface is busy and has not completed the previous command written to HVCON. Bit 1 and bit 2 are not valid.
BUSY = 0, High voltage interface is not busy and has completed the command written to HVCON. Bit 1 and bit 2 are valid.
Rev. PrD | Page 98 of 128
Preliminary Technical Data
High Voltage Data Register:
Name : Address : Default Value : Access : Function : HVDAT 0xFFFF080C 0x00 Read/Write
ADUC7032
HVDAT is a 12-bit register that is used to hold data to be written indirectly to and read indirectly from the following high voltage interface registers
Table 63: HVDAT MMR Bit Designations
Bit 11-8
Description Command to which High Voltage Data, HVDAT[7-0], is associated with. These bits are read only and should be written as zeros. 0x00 0x01 0x02 0x03 0x08 0x09 Read back high voltage register HVCFG0 into HVDAT Read back high voltage register HVCFG1 into HVDAT Read back high voltage status register HVSTA into HVDAT Read back high voltage status register HVMON into HVDAT Write the value in HVDAT to the high voltage register HVCFG0 Write the value in HVDAT to the high voltage register HVCFG1
7-0
High Voltage Data to Read/Write
Rev. PrD | Page 99 of 128
Preliminary Technical Data
High Voltage Configuration0 Register :
Name : Address : Default Value : Access : Function : HVCFG0 Indirectly addressed via the HVCON high voltage interface 0x00 Read/Write
ADUC7032
This 8-bit register controls the function of high voltage circuits on the ADUC7032. This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface. Data to be written to this register is loaded via the HVDAT MMR and data is read back from this register via the HVDAT MMR.
Table 64: HVCFG0 Bit Designations
Bit 7
Description Wake Thermal Shutdown Disable: This bit is set to 1 to disable the automatic shutdown of the Wake driver when a thermal event occurs. This bit is cleared to 0 to enable the automatic shutdown of the Wake driver when a thermal event occurs. Precision Oscillator Enable Bit This bit is set to 1 to enable the Precision, 131kHz oscillator. The oscillator start-up time is typically 70secs (including HV interface latency of 10secs) This bit is cleared to 0 to power down the Precision, 131kHz oscillator Reserved This bit is reserved and should be written as 0 by user code. WU Assert Bit This bit is set to 1 to assert the external WU pin high. This bit is cleared to 0 to pull the external WU pin low via an internal 10K pull-down resistor. PSM Enable Bit This bit is cleared to 0 to disable the Power Supply (Voltage at the VDD pin) Monitor This bit is set to 1 to enable the Power Supply (Voltage at the VDD pin) Monitor. If IRQ3 (IRQEN[16] is enabled the PSM will generate an interrupt if the voltage at the VDD pin drops below 6.0V. Low Voltage Flag Enable Bit This bit is cleared to 0 to disable the Low Voltage Flag function This bit is set to 1 to enable the Low Voltage Flag function. The Low Voltage Flag can be interrogated via HVMON[3] after power up to determine if the REG_DVDD voltage previously dropped below 2.1V LIN Operating Mode These bits enable/disable the LIN driver. 00 LIN Disabled
0 1 Reserved - (not LIN V2.0 compliant)
6
5 4
3
2
1-0
1 1
0 1
LIN Enabled Reserved
Rev. PrD | Page 100 of 128
Preliminary Technical Data
High Voltage Configuration1 Register :
Name : Address : Default Value : Access : Function : HVCFG1 Indirectly addressed via the HVCON high voltage interface 0x00 Read/Write
ADUC7032
This 8-bit register controls the function of high voltage circuits on the ADUC7032. This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface, data to be written to this register is loaded via HVDAT and data is read back from this register via HVDAT.
Table 65: HVCFG1 Bit Designations
Bit 7
Description Attenuator Enable Bit This bit is cleared to 0 to disable the internal voltage attenuator and attenuator buffer. This bit is set to 1 to enable the internal voltage attenuator and attenuator buffer. High Voltage Temperature Monitor The high voltage temperature monitor is an un-calibrated temperature monitor located on-chip close to the high voltage circuits. This monitor is completely separate to the on-chip, precision temperature sensor(controlled via ADC2CON[7,6]) and allows user code to monitor die temperature change close the hottest part of the ADUC7032 die. The monitor generates a typical output voltage of 600mV at 25C and has a negative temperature coefficient of typically -2.1mV/C This bit is set to 1 to enable the on-chip, high voltage temperature monitor. Once enabled this voltage out temperature monitor is routed directly to the temperature channel ADC. This bit is cleared to 0 to disable the on-chip, high voltage temperature monitor. Voltage Channel Short Enable Bit This bit is set to 1 to enable an internal short (at the attenuator, before ADC input buffer) on the voltage channel ADC and allow noise be measured as a self diagnostic test. This bit is cleared to 0 to disable an internal short on the voltage channel. WU Read Back Enable Bit This bit is cleared to 0 to disable input capability on the external WU pin This bit is set to 1 to enable input capability on the external WU pin. In this mode, a rising or falling edge transition on the WU pin will generate a high voltage interrupt. Once this bit is set, the state of the WU pin can be monitored via the HVMON register (HVMON[7]). HV-IO Enable Bit This bit is set to 1 to re-enable any High Voltage-IO pins (LIN/Wake) that have been disabled as a result of an short circuit current event(event must last longer than 20usecs for LIN Pin and 400usecs for Wake Pin). This bit must also be set to 1 to re-enable the Wake pin if disabled by a thermal event. It should be noted that this bit must be set to clear any pending interrupt generated by the short circuit event (even if the event has passed) as well as re-enabling the High-Voltage IO pins. Enable/Disable Short Circuit Protection (LIN) This bit is set to 1 to enable `passive' short circuit protection on LIN pin. In this mode, a short circuit event on the LIN pin will generate a HV interrupt (IRQ3-IRQEN[16]), assert the appropriate status bit in HVSTA but will NOT disable the short circuiting pin. This bit is cleared to 0 to enable `active' short circuit protection on LIN pin. In this mode, a short circuit event the LIN pin will generate a HV interrupt (IRQ3-IRQEN[16]), assert the appropriate status bit in HVSTA and automatically disable the short circuiting pin. Once disabled, the I/O pin can only be re-enabled by writing to HVCFG1[3]. WU Pin Time-Out ( MonoFlop ) Counter Enable/Disable This bit is set to disable the WU I/O time-out counter. This bit is cleared to enable a time-out counter which automatically de-asserts the WU pin 1.3 seconds after user code has asserted the WU pin via HVCFG0[4]. WU O/C Diagnostic Enable This bit is set to enable an internal WU I/O diagnostic pull-up resistor to the VDD pin thus allowing detection of an O/C condition on the WU pin. This bit is cleared to disable an internal WU I/O diagnostic pull-up resistor
6
5
4
3
2
1
0
Rev. PrD | Page 101 of 128
Preliminary Technical Data
High Voltage Interrupt Status Register :
Name : Address : Default Value : Access : Function : HVSTA Indirectly addressed via the HVCON high voltage interface 0x00 Read Only. This register should only be read on a high voltage interrupt.
ADUC7032
This 8-bit read only register reflects a change of state of all the corresponding bit in the HVMON register. This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface, and data is read back from this register via HVDAT. It should be noted that in response to a high voltage interrupt event, the high voltage interrupt controller simultaneously and automatically loads the current value of the high voltage Status register (HVSTA) into the HVDAT register
Table 66: HVSTA Bit Designations
Bit 7-6 5
Description Reserved These bits should not be used and are reserved for future use. PSM Status Bit (Only valid If enabled via HVCFG0[3]) This bit is 0 if the voltage at the VDD pin stays above 6.0V This bit will be 1 if the voltage at the VDD pin drops below 6.0V. Please note that this bit is not latched and the IRQ needs to be enabled to detect it. WU Request Status Bit (Only valid If enabled via HVCFG1[4]) Once enabled via HVCFG1[4], this bit will be set to 1 to indicate that a rising or falling edge transition on the WU pin generated a high voltage interrupt. Over Temperature (Always enabled) This bit will be 0 if a thermal shutdown event has not occurred. This bit will be 1 if a thermal shutdown event has occurred. LIN Short Circuit Status Flag This bit will be 0 during normal LIN operation This bit will be 1 if a LIN short circuit is detected. In this condition the LIN driver will be automatically disabled. Reserved This bit is reserved and should be written as 0 by user code. Wake Short Circuit Status Flag This bit will be 0 during normal Wake operation This bit will be 1 if a Wake short circuit is detected.
4
3
2
1 0
Rev. PrD | Page 102 of 128
Preliminary Technical Data
High Voltage Monitor Register :
Name : Address : Default Value : Access : Function : HVMON Indirectly addressed via the HVCON high voltage interface 0x00 Read Only
ADUC7032
This 8-bit read only register reflects the current status of enabled high voltage related circuits and functions on the ADUC7032. This register is not an MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface, and data is read back from this register via HVDAT.
Table 67: HVMON Bit Designations
Bit 7 6
Description WU Pin Diagnostic Read-back Once enabled via HVCFG1[4], this read only bit will reflect the state of the external WU pin. Over Temperature This bit will be 0 if a thermal shutdown event has not occurred. This bit will be 1 if a thermal shutdown event has occurred. Reserved This bit should not be used and is reserved for future use. Buffer Enabled This bit will be 0 if the Voltage Channel ADC input buffer is disabled This bit will be 1 if the Voltage Channel ADC input buffer is enabled
Low Voltage Flag Status Bit (Only valid If enabled via HVCFG0[2]) This bit will be 0 on power-on if REG_DVDD had dropped below 2.1V. In this state, RAM contents can be deemed corrupt. This bit will be 1 on power-on if REG_DVDD had not dropped below 2.1V. In this state, RAM contents can be deemed valid. It will only be cleared by re-enabling the Low Voltage Flag in HVCFG0[2] LIN Short Circuit Status Flag: This bit will be 0 if the LIN driver is operating normally. This bit will be 1 if the LIN driver has experienced a short circuit condition and will be cleared automatically by writing to HVCFG1[3].
5 4
3
2
1 0
Reserved These bits should not be used and are reserved for future use. Wake Short Circuit Status Flag: This bit will be 0 if the Wake driver is operating normally. This bit will be 1 is the Wake driver has experienced a short circuit condition.
Rev. PrD | Page 103 of 128
Preliminary Technical Data
WAKE-UP(WU)
The Wake Up pin is a high voltage GPIO controlled via HVCON and HVDAT.
ADUC7032
Wake-Up(WU) Pin Circuit Description
The WU pin is configured by default as an output with an internal 10K pull-down resistor and high side FET driver. The WU pin in its default mode of operation is specified to generate an active high system wake-up request by forcing the external system WU bus high. User code can assert the WU output by writing directly to HVCFG0[4].
VDD SHORT CIRCUIT PROTECTION OUTPUT CONTROL HVMON[0] 400s GLITCH IMMUNITY SHORT CIRCUIT TRIP REFERENCE INTERNAL SENSE RESISTOR
It should be noted the output will only respond after the 10usecs latency through the (serial communication based) high voltage interface
NORMAL HVCFG0[4]
HVCFG1[0] 6k O/C DIAGNOSTIC RESISTOR
EXTERNAL WU PIN EXTERNAL CURRENT-LIMIT RESISTOR 39 CLOAD 91nF RLOAD 1k
EXTERNAL WAKE BUS
NORMAL HVMON[7]
3V
R1 6.6k R2 3.3k
INTERNAL 10k RESISTOR
IO_VSS
Figure 36 : WU Circuit, Block Diagram
The internal FET is capable of sourcing significant current and therefore a substantial on-chip self-heating can occur if this driver is asserted for a long time period. For this reason a Monoflop, a 1.3 second timeout timer, has been included. By default the Monoflop is enabled and will disable the Wake Driver after 1.3 seconds. It is possible to disable the Monoflop via HVCFG1[1]. If the Wake Monoflop is disabled, then the Wake driver should be disabled after 1.3s. The Wake Pin also features a short circuit detection feature. When the wake Pin sources more than 200mA for 400uS a high voltage interrupt will be generated with HVMON[0] set.
By Default, a thermal shutdown event disables the Wake Driver. The Wake driver must be re-enabled manually after a thermal event via HVCFG1[3]. It is possible to disable the automatic shutdown during a thermal event via HVCFG0[7]. The WU pin can be configured in I/O mode by writing a 1 to HVCFG1[4]. In this mode, a rising or falling edge will immediately generate a high voltage interrupt. HVMON[7] directly reflects the state of the external WU pin. This comparator has a trip level of 3VTYP.
Rev. PrD | Page 104 of 128
05994-037
ENABLE READ-BACK HVCFG1[4]
Preliminary Technical Data
ADUC7032
HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE
An interrupt controller is also integrated with the high voltage circuits. If enabled via IRQEN[16], one of 5 high voltage sources can assert the high voltage interrupt (IRQ3) signal and interrupt the MCU core. While the MCU response to this interrupt event is, as normal, to vector to the IRQ or FIQ interrupt vector address. The high voltage interrupt controller simultaneously and automatically loads the current value of the high voltage Status register (HVSTA) into the HVDAT register. During this time the BUSY bit in HVCON[0] is set to indicate the transfer is in progress and will be cleared after 10usecs to indicate the HVSTA contents are now available in HVDAT. The interrupt handler can therefore poll the busy bit in HVCON until it de-asserts and then read the HVDAT register At this time HVDAT will then hold the value of the HVSTA register. The status flags can then be interrogated to determine the exact source of the high voltage interrupt and the appropriate action taken.
LOW VOLTAGE FLAG ( LVF )
The ADUC7032 features a Low Voltage flag, which when enabled allows the user to monitor REG_DVDD. When enabled via HVCFG0[2], the Low Voltage Flag may be monitored via HVMON[3]. If REG_DVDD drops below 2.1V, then HVMON[3] is cleared. If REG_DVDD drops below 2.1V the Ram contents are corrupted. Once the Low Voltage Flag is enabled, it is only reset by REG_DVDD dropping below 2.1V or the disabling of the LVF functionality via HVCFG0[2].
HIGH VOLTAGE DIAGNOSTICS
It is possible to diagnosis fault conditions on the Wake and LIN bus as follows.
Table 68: High Voltage Diagnostics
High Voltage Pin
Fault Condition
Short Between LIN and VBat
Method
Result
LIN Short Circuit interrupt will be generated after 20uS if more than 100mA is drawn continuously.
Drive LIN Low
LIN Short Between LIN and GND Short Between Wake and VBat Wake Short Between Wake and GND Open Circuit Drive LIN High
LIN Read back reads back low.
Drive Wake Low
Read Back high
Drive Wake High Enable OC Diagnostic Resistor with Wake disabled.
Wake Short Circuit interrupt will be generated after 400us if more than 200mA is sourced HVMON[7] will be cleared if load is connected and set if wake is open circuited
Rev. PrD | Page 105 of 128
Preliminary Datasheet
UART SERIAL INTERFACE
The ADUC7032 features a 16450 compatible UART. The UART is a full-duplex Universal Asynchronous Receiver/Transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the ARM7TDMI. The UART features a fractional divider, which facilitates high accuracy baud rate generation, and a network addressable mode. The UART functionality is made available on GPIO_5, RXD, and GPIO_6, TXD, of the ADUC7032: The serial communication adopts a asynchronous protocol that supports various word length, stop bits and parity generation options selectable in the configuration register.
ADUC7032
ADUC7032 Fractional divider:
The fractional divider combined with the normal baud-rate generator allows the generation of accurate, high speed, baudrates.
CORE CLOCK /2 FBEN
/(M+N/2048)
Figure 37 : Fractional Divider Baud Rate generation
Calculation of the baud rate using fractional divider is as follow:
BAUD RATE GENERATION
The ADUC7032 features two methods of generating the UART Baud Rate: 1. 2. Normal 450 UART baud rate generation. ADUC7032 Fractional Divider
Baudrate =
20.48MHz 2 CD x 16 x DL x 2 x ( M + N ) 2048
Equation 2 : Fractional Divider Baud Rate Generation Formula
M+
These two methods are explained in detail below.
N 20.48MHz = 2048 Baudrate x 2 CD x 16 x DL x 2
Normal 450 UART baud rate generation.
The baud rate is a divided version of the core clock using the value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
Table 70 gives some common baud rate values.
Table 70: Baud rate using the Fractional Baud rate generator
Baudrate =
20.48MHz 2 x16 x 2 x DL
CD
Baud rate 9600 19200 115200
CD
DL
M
N
05994-038
/16DL
UART
Actual Baud rate 9598.55 19197.09 115177.51
% error
Equation 1 : Standard Baud Rate Generator Formula
Table 69 gives some common baud rate values: Table 69 : Baud rate using the standard Baud rate generator Baud rate 9600 19200 115200 9600 19200 115200 CD DL Actual Baud rate 9552 19394 106667 10000 20000 80000 % error
0 0 0
42h 21h 5h
1 1 1
21 21 228
0.015% 0.015% 0.0195%
0 0 0 3 3 3
43h 21h 6h 8h 4h 1h
0.50% 1.01% 7.41% 4.17% 4.17% 30.56%
Rev. PrD | Page 106 of 128
Preliminary Technical Data
UART REGISTER DEFINITION
The UART interface consists of 9 registers namely:
ADUC7032
- COMTX: 8-bit transmit register - COMRX: 8-bit receive register - COMDIV0: divisor latch (low byte) COMTX, COMRX and COMDIV0 share the same address location. COMTX and COMTX can be accessed when bit 7 in COMCON0 register is cleared. COMDIV0 can be accessed when bit 7 of COMCON0 is set. COMDIV1: divisor latch (high byte) - COMCON0: line control register - COMSTA0: line status register - COMIEN0: interrupt enable register - COMIID0: interrupt identification register - COMDIV2: 16-bit fractional baud divide register
UART TX Register:
Name : Address : Default Value : Access : COMTX 0xFFFF0700 0x00 Write Only
UART Divisor Latch Register 0:
Name : Address : Default Value : Access : COMDIV0 0xFFFF0700 0x00 Read/Write
Function : This 8-bit register is written to, to transmit data via the UART.
Function : This 8-bit register contains the least significant byte of the divisor latch witch controls the baud rate at which the UART operates.
UART RX Register:
Name : Address : Default Value : Access : COMRX 0xFFFF0700 0x00 Read Only
UART Divisor Latch Register 1:
Name : Address : Default Value : Access : COMDIV1 0xFFFF0704 0x00 Read/Write
Function : This 8-bit register is read from to receive data transmitted via the UART.
Function : This 8-bit register contains the most significant byte of the divisor latch witch controls the baud rate at which the UART operates.
Rev. PrD | Page 107 of 128
Preliminary Technical Data
UART Control Register 0:
Name : Address : Default Value : Access : Function : COMCON0 0xFFFF070C 0x00 Read/Write This 8-bit register controls the operation of the UART in conjunction with COMCON1
ADUC7032
Table 71 : COMCON0 MMR Bit Descriptions
Bit 7
Name DLAB
Description
Divisor latch access Set by user to enable access to COMDIV0 and COMDIV1 registers
6
BRK
5
SP
4
EPS
3
PEN
2
STOP
1-0
WLS
Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX, COMTX and COMIEN0 Set break. Set by user to force TXD to 0 Cleared to operate in normal mode Stick parity Set by user to force parity to defined values: 1 if EPS = 1 and PEN = 1 0 if EPS = 0 and PEN = 1 Even parity select bit Set for even parity Cleared for odd parity Parity enable bit: Set by user to transmit and check the parity bit Cleared by user for no parity transmission or checking Stop bit Set by user to transmit 1.5 Stop bit if the Word Length is 5 bits or 2 Stop bits if the word length is 6, 7 or 8 bits. The receiver checks the first Stop bit only, regardless of the number of Stop bits selected Cleared by user to generate 1 Stop bit in the transmitted data Word length select: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
Rev. PrD | Page 108 of 128
Preliminary Technical Data
UART Control Register 1:
Name : Address : Default Value : Access : Function : COMCON1 0xFFFF0710 0x00 Read/Write This 8-bit register controls the operation of the UART in conjunction with COMCON0
Table 72 : COMCON1 MMR Bit Descriptions
ADUC7032
Bit 7-6
Name
Description UART Input Mux 00 RxD driven by LIN Input Reserved 01 10 RxD driven by GP5 Reserved 11 Reserved Required for LIN Communications via LIN pin Required for Serial communications via GP5 pin ( RxD )
5 4 3-0 LOOPBACK
Loop back Set by user to enable loop back mode. In loop back mode the TxD is forced high. Reserved
UART Status Register 0:
Name : Address : Default Value : Access : Function : COMSTA0 0xFFFF0714 0x60 Read Only This 8-bit read only register reflects the current status on the UART.
Table 73: COMSTA0 MMR Bit Descriptions
Bit 7 6
Name TEMT
Description Reserved COMTX empty status bit Set automatically if COMTX is empty Cleared automatically when writing to COMTX COMTX and COMRX empty Set automatically if COMTX and COMRX are empty Cleared automatically when one of the register receives data Break Indicator Set when SIN is held low for more than the maximum word length Cleared automatically Framing error Set when invalid stop bit Cleared automatically Parity error Set when a parity error occurs Cleared automatically Overrun error Set automatically if data are overwrite before been read Cleared automatically Data ready Set automatically when COMRX is full Cleared by reading COMRX
Rev. PrD | Page 109 of 128
5
THRE
4
BI
3
FE
2
PE
1
OE
0
DR
Preliminary Datasheet
UART Interrupt Enable Register 0:
Name : Address : Default Value : Access : Function : COMIEN0 0xFFFF0704 0x00 Read/Write The 8-bit register enables/disables the individual UART interrupt sources.
ADUC7032
Table 74 : COMIEN0 MMR Bit Descriptions
Bit 7-3 2
Name ELSI
Description Reserved and should be written as zeros RX status interrupt enable bit Set by user to enable generation of an interrupt if any of COMSTA0[3:0] are set Cleared by user Enable transmit buffer empty interrupt Set by user to enable interrupt when buffer is empty during a transmission Cleared by user Enable receive buffer full interrupt Set by user to enable interrupt when buffer is full during a reception Cleared by user
1
ETBEI
0
ERBFI
UART Interrupt Identification Register 0:
Name : Address : Default Value : Access : Function : Bit 2-1 Status bits 00 11 10 01 00 COMIID0 0xFFFF0708 0x01 Read Only This 8-bit register reflects the source of the UART interrupt
Table 75 : COMIID0 MMR Bit Descriptions
Bit 0 NINT 1 0 0 0 0
Priority
Definition No interrupt
Clearing operation
1 2 3 4
Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Reserved
Read COMSTA0 Read COMRX Write data to COMTX or read COMIID0
Rev. PrD | Page 110 of 128
Preliminary Technical Data
UART Fractional Divider Register:
Name : Address : Default Value : Access : Function : COMDIV2 0xFFFF072C 0x0000 Read/Write This 16-bit register controls the operation of the ADUC7032's fractional divider
ADUC7032
Table 76 : COMDIV2 MMR Bit Descriptions
Bit 15
Name FBEN
Description Fractional baud rate generator enable bit Set by user to enable the fractional baudrate generator Cleared by user to generate baudrate using the standard 450 UART baudrate generator Reserved M. if FBM = 0, M = 4 N
14-13 12-11 10-0 FBM[1-0] FBN[10-0]
Rev. PrD | Page 111 of 128
Preliminary Technical Data
SERIAL PERIPHERAL INTERFACE
The ADUC7032 features a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface which allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. The SPI interface is only operational with core clock divider bits (POWCON[2:0]= 0 or 1). The SPI Port can be configured for Master or Slave operation and consists of four pins, which are multiplexed with four GPIO. The four SPI pins are MISO, MOSI, SCLK and SS . The pins to which this signals are connected are shown in Table 77. SPIDIV register as follow:
ADUC7032
f serialclock =
20.48MHz 2 x (1 + SPIDIV )
Equation 3 : SPI Baud Rate Calculation
The maximum speed of the SPI clock is dependant on the clock divider bits and is summarized in Table 78.
Table 78: SPI speed vs. clock divider bits in master mode
CD bits SPIDIV
0 0x05 1.667
1 0x0B 0.833
Table 77 : SPI Output Pins
Max SCLK (MHz)
Pin GP0 ( GPIO MODE 1 ) GP1 ( GPIO MODE 1 ) GP2 ( GPIO MODE 1 ) GP3 ( GPIO MODE 1 )
Signal SS SCLK MISO MOSI
Description Chip Select Serial Clock Master Out, Slave In Master In, Slave Out In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 5.12 Mb at CD = 0. The formula to determine the maximum speed is as follow:
These signals are described in detail below.
f serialcloc k =
f HCLK 4
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first.
Equation 4 : Maximum Receive Baud Rate
In both master and slave modes, data is transmitted on one edge of the SCL signal and sampled on the other. Therefore, it is important that the polarity and phase are configured the same for the master and slave devices.
Chip Select (SS ) Input Pin MOSI (Master Out, Slave In Pin)
The MOSI (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first. In SPI Slave Mode, a transfer is initiated by the assertion of SS which is an active low input signal. The SPI port will then transmit and receive 8-bit data until the transfer is concluded by de-assertion of SS . In slave mode SS is always an input.
SPI registers definition
The following MMR registers are used to control the SPI interface: SPICON: 16-bit control register SPISTA: 8-bit read only status register SPIDIV: 8-bit serial clock divider register SPITX: 8-bit write only transmit register SPIRX: 8-bit read only receive register
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data being transmitted and received through the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in master mode and as an input in slave mode. In master mode polarity and phase of the clock are controlled by the SPICON register, and the bit-rate is defined in the
Rev. PrD | Page 112 of 128
Preliminary Technical Data
SPI Control Register :
Name : Address : Default Value : Access : Function : SPICON 0xFFFF0A10 0x0000 Read/Write The 16-bit MMR configures the Serial Peripheral Interface.
ADUC7032
Table 79 : SPICON MMR Bit Descriptions
Bit 15-13 12
Description Reserved and should be written as zero Continuous transfer enable Set by user to enable continuous transfer. In master mode the transfer will continue until no valid data is available in the TX register. SS will be asserted and remain asserted for the duration of each 8-bit serial transfer until TX is empty Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register then a new transfer is initiated after a stall period Loop back enable Set by user to connect MISO to MOSI and test software Cleared by user to be in normal mode Slave output enable Set by user to enable the slave output Cleared by user to disable slave output Slave select input enable Set by user in master mode to enable the output SPIRX overflow overwrite enable Set by user, the valid data in the RX register is overwritten by the new serial byte received Cleared by user, the new serial byte received is discarded SPITX underflow mode Set by user to transmit the previous data Cleared by user to transmit 0 Transfer and interrupt mode (master mode) Set by user to initiate transfer with a write to the SPITX register. Interrupt will occur when TX is empty Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt will occur when RX is full LSB first transfer enable bit Set by user the LSB is transmitted first Cleared by user the MSB is transmitted first Reserved and should be written as zero Serial clock polarity mode bit Set by user, the serial clock idles high Cleared by user the serial clock idles low Serial clock phase mode bit Set by user, the serial clock pulses at the beginning of each serial bit transfer Cleared by user, the serial clock pulses eat end of each serial bit transfer Master mode enable bit Set by user to enable master mode Cleared by user to enable slave mode SPI enable bit Set by user to enable the SPI Cleared to disable the SPI
11
10
9 8
7
6
5
4 3
2
1
0
Rev. PrD | Page 113 of 128
Preliminary Technical Data
SPI Status Register :
Name : Address : Default Value : Access : Function : SPISTA 0xFFFF0A00 0x00 Read Only The 8-bit MMR represents the current status of the Serial Peripheral Interface.
ADUC7032
Table 80 : SPISTA MMR Bit Descriptions
Bit 7-6 5
Description Reserved SPIRX data register overflow status bit Set if SPIRX is overflowing Cleared by reading SPISRX register SPIRX data register IRQ Set automatically if bit 3 or 5 are set Cleared by reading SPIRX register SPIRX data register full status bit Set automatically if a valid data is present in the SPIRX register Cleared by reading SPIRX register SPITX data register underflow status bit Set automatically if SPITX is under flowing Cleared by writing in the SPITX register SPITX data register IRQ Set automatically if bit 0 is clear or bit 2 is set Cleared by writing in the SPITX register or if finished transmission disabling the SPI SPITX data register empty status bit Set by writing to SPITX to send data. This bit is set during transmission of data Cleared when SPITX is empty
4
3
2
1
0
SPI Receive Register :
Name : Address : Default Value : Access : SPIRX 0xFFFF0A04 0x00 Read Only
SPI Divider Register :
Name : Address : Default Value : Access : SPIDIV 0xFFFF0A0C 0x1B Read/Write
Function : This 8-bit MMR contains the data received via the Serial Peripheral Interface.
Function : The 8-bit MMR represents the frequency of the Serial Peripheral Interface is operating at. For more information on the calculation of the baud rate, please refer to Equation 3 : SPI Baud Rate Calculation.
SPI Transmit Register :
Name : Address : Default Value : Access : SPITX 0xFFFF0A08 0x00 Write Only
Function : This 8-bit MMR is written to, to transmit data via the Serial Peripheral Interface. .
Rev. PrD | Page 114 of 128
Preliminary Technical Data
LIN (LOCAL INTERCONNECT NETWORK ) INTERFACE
The ADUC7032 features a high voltage physical interface between the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1-20KBaud, and is compatible with the LIN2.0 standard. The pull-up resistor required for a slave node is on-chip, reducing the need for external circuitry. The LIN protocol is emulated using the on-chip UART, an IRQ, a dedicated LIN Timer and the high voltage transceiver which is also incorporated on-chip. This is shown in Figure 38. The LIN is clocked from the Low Power Oscillator, for the Break Timer, and a 5MHz output from the PLL which is used for the synch byte timing.
ADUC7032
LIN MMR DESCRIPTION
The LIN Hardware Synchronization (LHS) functionality is controlled via five MMRs. The function of each MMR is described below:. LHSSTA: LHS Status Register. This MMR contains information flags which describe the current status on the interface. LHS Control Register 0. This MMR controls the configuration of the LHS Timer. LHS Start and Stop Edge Control Register Dictates which edge of the LIN Synchronization byte the LHS starts/stops counting. LHS Synchronization 16Bit Timer, which is controlled by LHSCON0. LHS Break Timer Register
LHSCON0: LHSCON1:
LHSVAL0: LHSVAL1:
LHS INTERRUPT IRQEN[7]
LHS INTERRUPT LOGIC FOUR LIN INTERRUPT SOURCES BREAK LHSSTA[0] ADUC7032 LHS HARDWARE START LHSSTA[1] STOP LHSSTA[2] BREAK ERROR LHSSTA[4] LIN ENABLE (INTERNAL PULL-UP) HVCFG0[5] INPUT VOLTAGE THRESHOLD REFERENCE VDD VDD
X
MASTER ECU PROTECTION DIODE EXTERNAL LIN PIN MASTER ECU PULL-UP
5MHz 131KHz
LHSVAL0 LHSVAL1
RxD ENABLE LHSCON0[8]
RxD ADUC7032 UART TxD GPIO12 GP2DAT[29 & GP2DAT21
LIN MODE HVCFG0[1:0] OVER VOLATGE PROTECTION CLOAD
SCR OUTPUT DISABLE GPIO12 FUNCTION SELECT GP2CON[20] INTERNAL SHORT CIRCUIT SENSE RESISTOR
SHORT-CIRCUIT CONTROL HVCFG1[2]
INTERNAL SHORT-CIRCUIT TRIP REFERENCE
IO_VSS
Figure 38 : LIN I/O, Block Diagram
Rev. PrD | Page 115 of 128
Preliminary Technical Data
LIN Hardware Synchronization Status Register :
Name : Address : Default Value : Access : Function : LHSSTA 0xFFFF0780 0x00 Read Only
ADUC7032
The LHS Status register is an 8-bit register whose bits reflect the current operating status of the ADUC7032 LIN interface.
Table 81 : LHSSTA MMR Bit Descriptions
Bit 7-6 5
Description Reserved These read-only bits are reserved for future use LHS Reset Complete Flag This bit is set to 1 by hardware to indicate a LHS Reset Command has completed successfully. This bit is cleared to 0, after user code reads the LHSSTA MMR
4
Break Field Error This bit is set to 1 by hardware and generates an LHS Interrupt (IRQEN[7]) when the 12-bit, Break Timer (LHSVAL1) register overflows to indicate the LIN bus has stayed low too long thus indicating a possible LIN bus error. This bit is cleared to 0, after user code reads the LHSSTA MMR
3
LHS Compare Interrupt This bit is set to 1 by hardware when the value in LHSVAL0 (LIN Synchronisation Bit Timer) = the value in the LHSCMP register. This bit is cleared to 0, after user code reads the LHSSTA MMR
2
Stop Condition Interrupt This bit is set to 1 by hardware when a stop condition is detected. This bit is cleared to 0, after user code reads LHSSTA MMR
1
Start Condition Interrupt This bit is set to 1 by hardware when a start condition is detected. This bit is cleared to 0, after user code reads LHSSTA MMR
0
Break Timer Compare Interrupt This bit is set to 1 by hardware when a valid LIN Break condition is detected. A LIN Break conditions is generated when the LIN Break Timer value reaches the Break timer compare value (see LHSVAL1 description below). This bit is cleared to 0, after user code reads the LHSSTA MMR
Rev. PrD | Page 116 of 128
Preliminary Technical Data
LIN Hardware Synchronization Control Register 0:
Name : Address : Default Value : Access : Function : LHSCON0 0xFFFF0784 0x0000 Read/Write
ADUC7032
The LHS Control register is a 16-bit register that in conjunction with the LHSCON1 register is used to configure the LIN mode of operation.
Table 82 : LHSCON0 MMR Bit Descriptions
Bit 15-12 11
Description Reserved These bits are reserved for future and should be written as 0 by user software. Break Timer Compare Interrupt Disable: This bit is set to 1 to disable the Break Timer Compare interrupt. This bit is cleared to 0 to enable the Break Timer Compare Interrupt
10
Break Timer Error Interrupt Disable: This bit is set to 1 to disable the Break Timer Error interrupt. This bit is cleared to 0 to enable the Break Timer Error Interrupt
9
LIN Transceiver, Stand-Alone Test Mode This bit is cleared to 0 by user code to operate the LIN in normal mode, driven directly from the on-chip UART. This bit is set to 1 by user code to enable external GPIO7 and GPIO8 pins to drive the LIN transceiver TxD and RxD respectively, independent of the UART. The functions of GPIO7 and GPIO8 should first be configured by user code via GPIO function select bits <0 and 4> in the GP2CON register.
8
Gate UART Bit This bit is set to 1 by user code to disable the internal UART RxD (receive data) by gating it high until both the break field and subsequent LIN Sync byte have been detected. This ensures the UART will not receive any spurious serial data during Break or Sync field periods which will have to be flushed out of the UART before valid data fields can start to be received. This bit is set to 0 by user code to enable the internal UART RxD (receive data) after the break field and subsequent LIN Sync byte have been detected so that the UART can receive the subsequent LIN data fields.
7
Sync Timer Stop Edge Type Bit This bit is cleared to 0 by user code to stop the sync timer on the falling edge count configured via the LHSCON1[7:4] register. This bit is set to 1 by user code to stop the sync timer on the rising edge count configured via the LHSCON1[7:4] register.
6-5 4
Reserved These bits are reserved for future and should be written as 0 by user software. Enable Stop Interrupt This bit is cleared to 0 by user code to disable interrupts when a stop condition occurs This bit is set to 1 by user code to generate an interrupt when a stop condition occurs
3
Enable Start Interrupt This bit is cleared to 0 by user code to disable interrupts when a start condition occurs This bit is set to 1 by user code to generate an interrupt when a start condition occurs
2
LIN Sync Enable Bit This bit is cleared to 0 by user code to disable LHS functionality This bit is set to 1 by user code to enable LHS functionality
1
Edge Counter Clear Bit This bit is cleared to 0 by user code to enable the rising or falling edge counters to function normally This bit is set to 1 by user code to clear the internal edge counters in the LHS peripheral, this bit does not reset to 0 automatically and requires user code to write 0 to re-enable the edge counters.
Rev. PrD | Page 117 of 128
Preliminary Technical Data
0 LHS Reset Bit This bit is cleared to 0 by user code to enable the LHS logic to function normally
ADUC7032
This bit is set to 1 by user code to reset all LHS logic to default conditions, the bit is cleared to 0 automatically in hardware.
LIN Hardware Synchronization Control Register 1:
Name : Address : Default Value : Access : Function : LHSCON1 0xFFFF078C 0x32 Read/Write The LHS Control register is an 8-bit register that in conjunction with the LHSCON0 register is used to configure the LIN mode of operation.
Table 83 : LHSCON1 MMR Bit Descriptions
Bit 7-4
Description LIN STOP Edge Count These 4 bits are set by user code to the number of falling or rising edges on which to stop the internal LIN synchronization counter. The stop value of this counter can be read by user code via LHSVAL0. The type of edge, either rising or falling, is configured by LHSCON0[7]. The default value of these bits is 0x3 which configures the hardware to stop counting on the third falling edge. It should be noted that the first falling edge is taken as the falling edge at the start of the LIN break pulse.
3-0
LIN START Edge Count These 4 bits are set by user code to the number of falling edges after which the internal LIN synchronization timer will start counting. The stop value of this counter can be read by user code via LHSVAL0. The default value of these bits is 0x2 which configures the hardware to start counting on the second falling edge. It should be noted that the first falling edge is taken as the falling edge at the start of the LIN break pulse.
LIN Hardware Synchronization Timer0 Register :
Name : Address : Default Value : Access : Function : LHSVAL0 0xFFFF0788 0x0000 Read/Write The 16-bit read only LHSVAL0 register holds the value of the internal LIN synchronization timer. The LIN synchronization timer is clocked from an internal 5MHz clock which is independent of Core clock and baud-rate frequency. In LIN mode, the value read by user code from the LHSVAL0 register can be used calculate the master LIN baud-rate. This calculation can then be used to configure the internal UART baud-rate to ensure correct LIN communication via the UART from the ADUC7032 slave to the LIN master node.
Rev. PrD | Page 118 of 128
Preliminary Technical Data
LIN Hardware Break Timer1 Register :
Name : Address : Default Value : Access : Function : LHSVAL1 0xFFFF0790 0x000(read) or 0x047(write) Read/Write
ADUC7032
When user code reads this location, the 12-bit value returned is the value of the internal LIN break timer, which is clocked directly from the on-chip low power (131KHz) oscillator and times the LIN Break pulse. A negative edge on the LIN bus or user code reading the LHSVAL1 will result in the timer and the register contents being reset to 0. When user code writes to this location, the 12-bit value is actually written not to the LIN Break timer but to a LIN Break Compare register. In LIN mode of operation the value in the compare register is continuously compared to the break timer value. A LIN Break interrupt (IRQEN[7] and LHSSTA[0]) is generated when the timer value reaches the compare value. After the Break Condition interrupt, the LIN Break timer continues to count until the rising edge of the Break signal. If a rising edge is not detected and the 12-bit timer overflows (4096 X 1/131KHz= 31msecs), a Break Field Error Interrupt (IRQEN[7] and LHSSTA[4]) will be generated. By default, the value in the compare register is 0x47, this corresponds to 11 X Bit periods i.e. the minimum pulse width for a LIN break pulse at 20kbps. For different baud rates, this value may be changed by writing to. It is also important to note that if a valid break interrupt is not received then subsequent Sync pulse timing via LHSVAL0 register will not occur.
LIN HARDWARE INTERFACE
LIN Frame Protocol
The LIN frame protocol is broken into 4 main categories: * * * * Break Symbol SYNC Byte Protected Identifier Data Bytes The format of the frame header, Break, Synchronization Byte and Protected Identifier are shown in Figure 39. Essentially, the embedded UART, LIN Hardware Synchronization logic and the high voltage transceiver interface all combine on-chip to support and manage LIN based transmissions and receptions.
> = 14TBIT 13TBIT
>1TBIT
2TBIT
8TBIT 2TBIT
2TBIT
2TBIT
STA S0
S1
S2
S3
S4
S5
S6
S7 STO
05994-042
BREAK
SYNC
PROTECTED ID
Figure 39 : LIN Interface Timing
Rev. PrD | Page 119 of 128
Preliminary Technical Data
LIN Frame Break Symbol
As shown in Figure 40, the LIN "break" symbol is used to signal the start of a new frame. It lasts at least 13 bit periods and a slave must be able to detect a "break" symbol, even if it expects data or is in the process of receiving data. The ADUC7032 accomplishes this by using the LHSVAL1 Break Condition and
ADUC7032
Break Error detect functionality as described earlier. The "break" period does not have to be accurately measured, but if a bus fault condition (bus held low) occurs it must be flagged.
TBREAK > 13TBIT
Figure 40 : LIN Break Field
LIN Frame Synchronization Byte
The baud rate of the communication via LIN is calculated from the SYNC Byte. This can be seen in Figure 41. The time between the first falling edge of the Sync Field and the fifth falling edge of the Sync Field is measured. This is then divided
TBIT
by eight to give the baud rate of the data that will be transmitted. The ADUC7032 implements the timing of this Sync byte in hardware. For more information on this feature, please refer to LIN Hardware Synchronization.
START BIT
STOP BIT
Figure 41 : LIN Synch byte Field
LIN Frame Protected Identifier
After receiving the LIN synch field, the required baud rate for the UART is calculated. The UART is then configured, which allows the ADUC7032 to receive the Protected Identifier, as shown in Figure 42. The Protected Identifier consists of two sub-fields, the identifier and the identifier parity. The six bit identifier contains the identifier of the target for the frame. The
TBIT START BIT ID0 ID1 ID2 ID3 ID4 ID5 P0 P1 STOP BIT
05994-045
identifier signifies the number of data bytes to be either received or transmitted. The number of bytes is user configurable at system level design. The parity is calculated on the identifier, and is dependent on the revision of LIN the system is designed for.
Figure 42 : LIN Identifier Byte Field
Rev. PrD | Page 120 of 128
05994-044
05994-043
START BIT
BREAK DELIMIT
Preliminary Technical Data
LIN Frame Data Byte
The data byte frame carries between one and eight bytes of data. The number of bytes contained in the frame will be
TBIT START BIT BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 STOP BIT
05994-046
ADUC7032
dependent on the LIN Master. The data byte frame is split into data bytes as shown in Figure 43.
Figure 43 : LIN Data Byte Field
LIN Frame Data Transmission and Reception
Once the Break Symbol and Synchronization Byte have being correctly received, data is transmitted and received via the COMTX and COMRX MMRs, after configuration of the UART to the required Baud Rate. To configure the UART for use with LIN requires the use of the following UART MMRs: - COMDIV0: divisor latch (low byte) - COMDIV1: divisor latch (high byte) - COMDIV2: 16-bit fractional baud divide register The required values for COMDIV0, COMDIV1 and COMDIV2 are derived from the LHSVAL0, to generate the required baud rate.. - COMCON0: line control register Once the UART is correctly configured, the LIN protocol for receiving and transmitting data is identical to the UART specification. To manage data on the LIN bus requires use of the following UART MMRs: -
COMTX: 8-bit transmit register COMRX: 8-bit receive register COMCON0: line control register COMSTA0: line status register
To transmit data on the LIN bus requires that the relevant data be placed into COMTX. To read data received on the LIN bus requires the monitoring of COMRX. To ensure that data is received or transmitted correctly COMSTA0 is monitored. For more information please refer to the UART section of the datasheet. Under software control it is possible to multiplex the UART data lines (TxD and RxD) to external GPIO pins (GPIO_7 and GPIO_8). For more information please refer to the description of the GPIO Port1 Control Register (GP1CON).
Rev. PrD | Page 121 of 128
Preliminary Technical Data
Example LIN Hardware Synchronization Routine
Consider the following C-Source Code LIN Initialization Routine.
ADUC7032
void LIN_INIT(void ) { char HVstatus; GP2CON = 0x110000;// Enable LHS on GPIO Pins LHSCON0 = 0x1; // Reset LHS Interface do{ HVDAT = 0x02; // Enable Normal LIN TX mode HVCON = 0x08; // Write to Config0 do{ HVstatus = HVCON; } while(HVstatus & 0x1); // Wait until command is finished } while (!(HVstatus & 0x4)); // transmit command is correct while((LHSSTA & 0x20) == 0 ) { // Wait until the LHS Hardware is reset } LHSCON1 // // LHSCON0 // // // // // LHSVAL1 // = 0x062; // Sets Stop Edge as the fifth falling edge and the start edge as the first falling edge in the sync byte = 0x0114; // Gates UART RX Line, ensure no interference from the LIN into the UART. Selects the stop condition as a falling edge Enables Generation of an interrupt on the stop condition. Enables the interface = 0x03F; // Set number of 131kHz periods to generate a Break Interrupt 0x3F / 131kHz ~ 480us which is just over 9.5 TBits. } falling edges is received, a STOP condition interrupt is generated. It is at this point that the UART is configured to received the Protected Identifier. The UART must not be ungated, via LHSCON0[8], before the LIN bus returns high. If this occurs, UART communication errors may occur. Example code to ensure this is shown below: This process is shown in detail in Figure 44.
Using this configuration, LHSVAL1 begins to count on the first falling edge received on the LIN bus. If LHSVAL1 exceeds the value written to LHSVAL1, in this case 0x3f, a Break Compare interrupt is generated. ON the next falling edge, LHSVAL0 begins counting. LHSVAL0 monitors the number of falling edges and compares this to the value written to LHSCON1, in this example the number of edges to monitor is the sixth falling edge of the LIN frame, or the fifth falling edge of the SYNC byte. Once this number of while((GP2DAT & 0x10 ) {} // LHSCON0 = 0x4; // // IRQEN = 0x800; // //
== 0 ) Wait until LIN Bus returns High Enable LHS to detect Break Condition Ungate RX Line Disable all interrupts except Break Compare Interrupt Enable UART Interrupt The UART is now configured and ready to be used for LIN
Rev. PrD | Page 122 of 128
Preliminary Technical Data
ADUC7032
LHSVAL1 RESET AND STARTS COUNTING
BREAK COMPARE INTERRUPT GENERATED
LHSVAL0 STARTS COUNTING
LHSVAL0 STOPS UART CONFIGURED BEGIN COUNTING. STOP LHS INTERRUPTS RECEIVING DATA INTERRUPT DISABLED EXCEPT VIA UART GENERATED BREAK COMPARE
TBIT
START BIT
STOP BIT
START ID0 BIT
ID1
ID2
ID3
ID4
ID5
P0
P1
STOP BIT
05994-047
LHSVAL1 = 0x3F
Figure 44 : Example LIN Configuration
LIN Diagnostics
The ADUC7032 features the capability to non-intrusively monitor the current state of the LIN pin. This read back functionality is implemented via GPIO11. The current state of the LIN pin is contained in GP2DAT[4] It is also possible to drive the LIN pin high and low via user software, allowing the user to detect open circuit conditions. This functionality is implemented via GPIO12. To enable this functionality GPIO12 must be configured as a GPIO via GP2CON[20]. Once configured, the LIN pin may be pulled high or low via GP2DAT. The ADUC7032 also features short circuit protection on the LIN pin. If a short circuit condition is detected on the LIN pin, HVSTA[2] is set. This bit is cleared by re-enabling the LIN driver via HVCFG1[3]. It is possible to disable this feature via HVCFG1[2].
Rev. PrD | Page 123 of 128
Preliminary Technical Data
ADUC7032 ON-CHIP DIAGNOSTICS
ADUC7032
The ADUC7032 integrates multiple diagnostic support circuits on-chip. These circuits allow the device to test core digital functionality, analog front-end and high-voltage I/O ports in-circuit.
ADC Diagnostics
Internal Test Voltage The current channel can be configured to convert on an internal 8.3mV test voltage . On any gain range the result should be within 0.5% of the expected result. Internal Short Mode The current and voltage input channels can also be shorted internally. Converting on the internal short will allow an assessment of the internal ADC noise to be determined. Internal Current Sources Internal current sources can also be enabled on both current and temperature channels. These current sources can be used to determine external short or open circuit conditions in both external shunt or temperature sensor configurations.
High Voltage I/O Diagnostics
High Voltage I/O Read back All high voltage I/O pins are supported with read back capability. This allows the detection of external short conditions. High Voltage Current Detection All high voltage I/O pins also have a high current detection capability allowing high side connections to VBAT to be detected and controlled.
Rev. PrD | Page 124 of 128
Preliminary Technical Data
PART IDENTIFICATION
Two registers mapped into the MMR space are intended to allow user code identify and trace, manufacturing lot ID information, part ID number, silicon mask revision and kernel
ADUC7032
revision. This information is contained in the SYSSER0 and SYSSER1 MMR which are described in detail below..
System Serial ID Register 0:
Name : Address : Default Value : Access : Function : SYSSER0 0xFFFF0238 0x00000000(Updated by kernel at power-on) Read/Write At power-on, this 32-bit register will hold the value of the original manufacturing lot number from which this specific ADUC7032 unit was manufactured (bottom die only). Used in conjunction with SYSSER1, this lot number will allow the full manufacturing history of this part to be traced.
Table 84 : SYSSER0 MMR Bit Descriptions
Bit 31-27
Description Wafer Number: The 5 bits read from this location will give the wafer number ( 1-24 ) from the Wafer Fabrication Lot ID which this device came from , and when used in conjunction with SYSSER0[26-0] provides individual wafer traceability.
26-22
Wafer Lot Fabrication Plant The 5 bits read from this location reflect the manufacturing plant associate with this Wafer Lot, and used in conjunction with SYSSER0[21-0] provides wafer lot traceability.
21-16
Wafer Lot fabrication ID The 6 bits read from this location form part of the Wafer Lot Fabrication ID, and used in conjunction with SYSSER0[26-22] and SYSSER0[15-0] provides wafer lot traceability. Wafer Lot Fabrication ID These 16 LSBs will hold a 16-bit number which should be interpreted as the Wafer Fabrication Lot ID number. When used in conjunction with the value in SYSSER1 i.e. the manufacturing lot ID, this number is a unique identifier for the part.
15-0
Rev. PrD | Page 125 of 128
Preliminary Technical Data
System Serial ID Register 1:
Name : Address : Default Value : Access : Function : SYSSER1 0xFFFF023C 0x00000000(Updated by kernel at power-on) Read/Write
ADUC7032
At power-on, this 32-bit register will hold the values of the part ID number, silicon mask revision number and kernel revision number (bottom die only) as detailed below.
Table 85: SYSSER1 MMR Bit Descriptions
Bit 31-28
Description Silicon Mask Revision ID The 4 bits read from this nibble reflect the silicon mask ID number. Specifically, the hex value in this nibble should be decoded as the lower hex nibble in the hex numbers reflecting the ASCII characters in the range `A' to `O'. Examples:
Bits 19-16 = 0001 = 1hex, therefore this value should be interpreted as 41 which is ASCII character A corresponding to silicon mask revision A Bits 19-16 = 1011 = Bhex, therefore the number is interpreted as 4B which is ASCII character K corresponding to silicon mask revision K
27-20 The allowable range for this value is 1 to 15 which is interpreted as 41 to 4F or A to O) Kernel Revision ID This byte contains the hex number which should be interpreted as an ASCII character indicating the revision of the kernel firmware embedded in the on-chip Flash/EE memory. Example: Reading 0x41 from this byte should be interpreted as A indicating a revision A kernel is on-chip. 19-16 15-0
Kernel Minor Revision number For PreProduction Release, these bits refer to the Device's Kernel Minor Revision Number
Part ID These 16 LSBs will hold a 16-bit number which should be interpreted as the part ID number. When used in conjunction with the value in SYSSER0 i.e. the manufacturing lot ID, this number is a unique identifier for the part.
System Kernel Checksum:
Name : Address : Default Value : Access : Function : SYSCHK 0xFFFF0240 0x00000000(Updated by kernel at power-on) Read/Write At power-on, this 32-bit register will hold the kernel checksum
Rev. PrD | Page 126 of 128
Preliminary Technical Data
System Identification FEE0ADR:
Name : Address : Default Value : Access : Function : Note: FEE0ADR 0xFFFF0E10 Non Zero Read/Write Access
ADUC7032
This 16-bit register dictates the address upon which any Flash/EE command executed via FEExCON will act upon. This MMR is also used to identify ADuC7030 Family member and pre-release silicon revision.
Table 86: FEE0ADR System Identification MMR Bit Descriptions
Bit 15-12 11-8 7-4
Description Reserved Reserved Silicon Revision 0x0 0x1 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xD Others Type6 Type6X Type7OP Type8 Type7OP1 Type7M Type7 Type8W Type9 Type8V Reserved ADuC7030 ADuC7031 ADUC7032 ADuC7033 Reserved
3-0
ADuC7030 Family ID 0x0 0x1 0x2 0x3 Others
Rev. PrD | Page 127 of 128
Preliminary Technical Data
OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
48 1
PIN 1
ADUC7032
9.00 BSC SQ
37 36
1.45 1.40 1.35
TOP VIEW
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
(PINS DOWN)
7.00 BSC SQ
0.15 0.05
12 13 24
25
SEATING PLANE
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
Figure 45 : 48-Lead, Plastic Quad Flat Pack, (LQFP-48), Dimensions shown in millimeters
Rev. PrD | Page 128 of 128
PR05986-0-10/06(PrD)

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